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Date:   Thu, 5 Sep 2019 04:26:10 -0700
From:   Christoph Hellwig <hch@...radead.org>
To:     Andrew Murray <andrew.murray@....com>
Cc:     Dilip Kota <eswara.kota@...ux.intel.com>, jingoohan1@...il.com,
        gustavo.pimentel@...opsys.com, lorenzo.pieralisi@....com,
        robh@...nel.org, martin.blumenstingl@...glemail.com,
        linux-pci@...r.kernel.org, hch@...radead.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        andriy.shevchenko@...el.com, cheol.yong.kim@...el.com,
        chuanhua.lei@...ux.intel.com, qi-ming.wu@...el.com
Subject: Re: [PATCH v3 2/2] dwc: PCI: intel: Intel PCIe RC controller driver

On Thu, Sep 05, 2019 at 11:45:18AM +0100, Andrew Murray wrote:
> > +        depends on OF
> > +        select PCIE_DW_HOST
> > +        help
> > +          Say 'Y' here to enable support for Intel AHB/AXI PCIe Host
> > +	  controller driver.
> > +	  The Intel PCIe controller is based on the Synopsys Designware
> > +	  pcie core and therefore uses the Designware core functions to
> > +	  implement the driver.
> 
> I can see this description is similar to others in the same Kconfig,
> however I'm not sure what value a user gains by knowing implementation
> details - it's helpful to know that PCIE_INTEL_AXI is based on the
> Designware core, but is it helpful to know that the Designware core
> functions are used?

Not really.  What would be extremely useful for a user is what Intel
SOC contains this IP block, or the fact that most of those were
actually produced by Lantiq, a company bought by Intel.

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