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Message-ID: <e8ead144-dd4a-0ffc-6266-920f045250f3@linux.intel.com>
Date: Fri, 6 Sep 2019 18:39:43 +0800
From: Dilip Kota <eswara.kota@...ux.intel.com>
To: "Chuan Hua, Lei" <chuanhua.lei@...ux.intel.com>,
jingoohan1@...il.com, gustavo.pimentel@...opsys.com,
lorenzo.pieralisi@....com, robh@...nel.org,
martin.blumenstingl@...glemail.com, linux-pci@...r.kernel.org,
hch@...radead.org, devicetree@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, andriy.shevchenko@...el.com,
cheol.yong.kim@...el.com, qi-ming.wu@...el.com
Subject: Re: [PATCH v3 1/2] dt-bindings: PCI: intel: Add YAML schemas for the
PCIe RC controller
Hi Chuan Hua,
On 9/5/2019 10:23 AM, Chuan Hua, Lei wrote:
> Hi Dilip,
>
> On 9/4/2019 6:10 PM, Dilip Kota wrote:
>> The Intel PCIe RC controller is Synopsys Designware
>> based PCIe core. Add YAML schemas for PCIe in RC mode
>> present in Intel Universal Gateway soc.
>>
>> Signed-off-by: Dilip Kota <eswara.kota@...ux.intel.com>
>> ---
>> changes on v3:
>> Add the appropriate License-Identifier
>> Rename intel,rst-interval to 'reset-assert-us'
> rst->interval to reset-assert-ms(should be typo error)
Sure, i will fix it. That's a typo error.
Thanks for pointing it.
Regards
Dilip
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