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Message-ID: <VI1PR0402MB3485E83188A0972A2DA74C5D98BA0@VI1PR0402MB3485.eurprd04.prod.outlook.com>
Date:   Fri, 6 Sep 2019 10:36:54 +0000
From:   Horia Geanta <horia.geanta@....com>
To:     Andrey Smirnov <andrew.smirnov@...il.com>,
        Herbert Xu <herbert@...dor.apana.org.au>,
        Shawn Guo <shawnguo@...nel.org>
CC:     Cory Tusar <cory.tusar@....aero>, Chris Healy <cphealy@...il.com>,
        Lucas Stach <l.stach@...gutronix.de>,
        Iuliana Prodan <iuliana.prodan@....com>,
        "linux-crypto@...r.kernel.org" <linux-crypto@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        dl-linux-imx <linux-imx@....com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH] arm64: dts: imx8mq: Add CAAM node

On 8/31/2019 12:01 AM, Andrey Smirnov wrote:
> Add node for CAAM - Cryptographic Acceleration and Assurance Module.
> 
> Signed-off-by: Horia Geantă <horia.geanta@....com>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@...il.com>
> Cc: Cory Tusar <cory.tusar@....aero>
> Cc: Chris Healy <cphealy@...il.com>
> Cc: Lucas Stach <l.stach@...gutronix.de>
> Cc: Herbert Xu <herbert@...dor.apana.org.au>
> Cc: Shawn Guo <shawnguo@...nel.org>
> Cc: Iuliana Prodan <iuliana.prodan@....com>
> Cc: linux-crypto@...r.kernel.org
> Cc: linux-kernel@...r.kernel.org
> ---
> 
> Shawn:
> 
> Just a bit of a context: as per this thread
> https://lore.kernel.org/linux-crypto/20190830131547.GA27480@gondor.apana.org.au/
> I am hoping I can get and Ack from you for this patch, so it can go
> via cryptodev tree.
> 
Could we please get an Ack in time for v5.4?

Thanks,
Horia

> Thanks,
> Andrey Smirnov
> 
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 30 +++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index d09b808eff87..752d5a61878c 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -728,6 +728,36 @@
>  				status = "disabled";
>  			};
>  
> +			crypto: crypto@...00000 {
> +				compatible = "fsl,sec-v4.0";
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0x30900000 0x40000>;
> +				ranges = <0 0x30900000 0x40000>;
> +				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_AHB>,
> +					 <&clk IMX8MQ_CLK_IPG_ROOT>;
> +				clock-names = "aclk", "ipg";
> +
> +				sec_jr0: jr@...0 {
> +					compatible = "fsl,sec-v4.0-job-ring";
> +					reg = <0x1000 0x1000>;
> +					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> +				};
> +
> +				sec_jr1: jr@...0 {
> +					compatible = "fsl,sec-v4.0-job-ring";
> +					reg = <0x2000 0x1000>;
> +					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> +				};
> +
> +				sec_jr2: jr@...0 {
> +					compatible = "fsl,sec-v4.0-job-ring";
> +					reg = <0x3000 0x1000>;
> +					interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> +				};
> +			};
> +
>  			i2c1: i2c@...20000 {
>  				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
>  				reg = <0x30a20000 0x10000>;
> 

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