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Message-ID: <20190916113255.GA4352@sirena.co.uk>
Date: Mon, 16 Sep 2019 12:32:55 +0100
From: Mark Brown <broonie@...nel.org>
To: "Ramuthevar,Vadivel MuruganX"
<vadivel.muruganx.ramuthevar@...ux.intel.com>
Cc: robh+dt@...nel.org, mark.rutland@....com,
linux-spi@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, cheol.yong.kim@...el.com,
qi-ming.wu@...el.com
Subject: Re: [PATCH v1 2/2] spi: cadence-qspi: Add QSPI support for Intel LGM
SoC
On Mon, Sep 16, 2019 at 03:38:43PM +0800, Ramuthevar,Vadivel MuruganX wrote:
> Existing cadence drivers do not support SPI-NAND, it only supports to
> SPI-NOR and SPI devices. To state that is the driver for the same IP
> but due to different SPI flash memory(NAND) need to write from scratch.
What makes you say you need to write a separate driver? It's perfectly
possible to support the normal and flash I/O mechanisms in a single
driver and as well as the maintainence issues obviously someone could
build a system with both flash and non-flash devices on the same SPI
controller.
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