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Message-ID: <20190917155426.7432-21-tudor.ambarus@microchip.com>
Date: Tue, 17 Sep 2019 15:55:45 +0000
From: <Tudor.Ambarus@...rochip.com>
To: <vigneshr@...com>, <boris.brezillon@...labora.com>,
<marek.vasut@...il.com>, <miquel.raynal@...tlin.com>,
<richard@....at>, <linux-mtd@...ts.infradead.org>
CC: <dwmw2@...radead.org>, <computersforpeace@...il.com>,
<joel@....id.au>, <andrew@...id.au>, <matthias.bgg@...il.com>,
<vz@...ia.com>, <linux-arm-kernel@...ts.infradead.org>,
<linux-aspeed@...ts.ozlabs.org>, <linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>, <Tudor.Ambarus@...rochip.com>
Subject: [PATCH 20/23] mtd: spi-nor: Update sr2_bit7_quad_enable()
From: Tudor Ambarus <tudor.ambarus@...rochip.com>
Rename the method to spi_nor_sr2_bit7_quad_enable(). Do the
read back test on all the eight bits of the Status Register,
not just the QE one.
Signed-off-by: Tudor Ambarus <tudor.ambarus@...rochip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 8648666fb9bd..a9cdb6dbc25c 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1994,7 +1994,7 @@ static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
}
/**
- * sr2_bit7_quad_enable() - set QE bit in Status Register 2.
+ * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
* @nor: pointer to a 'struct spi_nor'
*
* Set the Quad Enable (QE) bit in the Status Register 2.
@@ -2005,10 +2005,11 @@ static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
*
* Return: 0 on success, -errno otherwise.
*/
-static int sr2_bit7_quad_enable(struct spi_nor *nor)
+static int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
{
u8 *sr2 = nor->bouncebuf;
int ret;
+ u8 sr2_written;
/* Check current Quad Enable bit value. */
ret = spi_nor_read_sr2(nor, sr2);
@@ -2025,13 +2026,15 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
if (ret)
return ret;
+ sr2_written = *sr2;
+
/* Read back and check it. */
ret = spi_nor_read_sr2(nor, sr2);
if (ret)
return ret;
- if (!(*sr2 & SR2_QUAD_EN_BIT7)) {
- dev_err(nor->dev, "SR2 Quad bit not set\n");
+ if (*sr2 != sr2_written) {
+ dev_err(nor->dev, "Read back test failed\n");
return -EIO;
}
@@ -3605,7 +3608,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
case BFPT_DWORD15_QER_SR2_BIT7:
nor->flags &= ~SNOR_F_HAS_16BIT_SR;
- flash->quad_enable = sr2_bit7_quad_enable;
+ flash->quad_enable = spi_nor_sr2_bit7_quad_enable;
break;
case BFPT_DWORD15_QER_SR2_BIT1:
--
2.9.5
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