linux-kernel - Re: [PATCH V3 1/4] clk: imx: pll14xx: avoid glitch when set rate

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Message-Id: <20190918060723.61E0120856@mail.kernel.org>
Date:   Tue, 17 Sep 2019 23:07:22 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     "festevam@...il.com" <festevam@...il.com>,
        "mturquette@...libre.com" <mturquette@...libre.com>,
        "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        Peng Fan <peng.fan@....com>
Cc:     "kernel@...gutronix.de" <kernel@...gutronix.de>,
        dl-linux-imx <linux-imx@....com>,
        Anson Huang <anson.huang@....com>,
        Jacky Bai <ping.bai@....com>, Abel Vesa <abel.vesa@....com>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Leonard Crestez <leonard.crestez@....com>,
        Peng Fan <peng.fan@....com>
Subject: Re: [PATCH V3 1/4] clk: imx: pll14xx: avoid glitch when set rate

Quoting Peng Fan (2019-09-08 20:39:34)
> From: Peng Fan <peng.fan@....com>
> 
> According to PLL1443XA and PLL1416X spec,
> "When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to
> output unstable clock until lock time passes. PLL1416X/PLL1443XA may
> generate a glitch at FOUT."
> 
> So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch.
> In the end of set rate, BYPASS will be cleared.
> 
> When prepare clock, also need to take care to avoid glitch. So
> we also follow Spec to set BYPASS before RESETB changed from 0 to 1.
> And add a check if the RESETB is already 0, directly return 0;
> 
> Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
> Reviewed-by: Leonard Crestez <leonard.crestez@....com>
> Signed-off-by: Peng Fan <peng.fan@....com>
> ---

Applied to clk-next