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Message-Id: <20190918060727.80D9620856@mail.kernel.org>
Date:   Tue, 17 Sep 2019 23:07:26 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     "festevam@...il.com" <festevam@...il.com>,
        "mturquette@...libre.com" <mturquette@...libre.com>,
        "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        Peng Fan <peng.fan@....com>
Cc:     "kernel@...gutronix.de" <kernel@...gutronix.de>,
        dl-linux-imx <linux-imx@....com>,
        Anson Huang <anson.huang@....com>,
        Jacky Bai <ping.bai@....com>, Abel Vesa <abel.vesa@....com>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Leonard Crestez <leonard.crestez@....com>,
        Peng Fan <peng.fan@....com>
Subject: Re: [PATCH V3 2/4] clk: imx: clk-pll14xx: unbypass PLL by default

Quoting Peng Fan (2019-09-08 20:39:39)
> From: Peng Fan <peng.fan@....com>
> 
> When registering the PLL, unbypass the PLL.
> The PLL has two bypass control bit, BYPASS and EXT_BYPASS.
> we will expose EXT_BYPASS to clk driver for mux usage, and keep
> BYPASS inside pll14xx usage. The PLL has a restriction that
> when M/P change, need to RESET/BYPASS pll to avoid glitch, so
> we could not expose BYPASS.
> 
> To make it easy for clk driver usage, unbypass PLL which does
> not hurt current function.
> 
> Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
> Reviewed-by: Leonard Crestez <leonard.crestez@....com>
> Signed-off-by: Peng Fan <peng.fan@....com>
> ---

Applied to clk-next

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