linux-kernel - [PATCH 4/4] ARM: dts: aspeed: ast2600: Add SCU interrupt controllers

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <1569341672-27632-5-git-send-email-eajames@linux.ibm.com>
Date:   Tue, 24 Sep 2019 11:14:32 -0500
From:   Eddie James <eajames@...ux.ibm.com>
To:     linux-kernel@...r.kernel.org
Cc:     devicetree@...r.kernel.org, linux-aspeed@...ts.ozlabs.org,
        andrew@...id.au, joel@....id.au, mark.rutland@....com,
        robh+dt@...nel.org, maz@...nel.org, jason@...edaemon.net,
        tglx@...utronix.de, Eddie James <eajames@...ux.ibm.com>
Subject: [PATCH 4/4] ARM: dts: aspeed: ast2600: Add SCU interrupt controllers

Add nodes for the interrupt controllers provided by the SCU.

Signed-off-by: Eddie James <eajames@...ux.ibm.com>
---
 arch/arm/boot/dts/aspeed-g6.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 3a1422f..d89f1e6 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -159,6 +159,24 @@
 					compatible = "aspeed,ast2600-smpmem";
 					reg = <0x180 0x40>;
 				};
+
+				scu_ic0: interrupt-controller@0 {
+					#interrupt-cells = <1>;
+					compatible = "aspeed,ast2600-scu-ic0";
+					reg = <0x560 0x4>;
+					interrupt-parent = <&gic>;
+					interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+					interrupt-controller;
+				};
+
+				scu_ic1: interrupt-controller@1 {
+					#interrupt-cells = <1>;
+					compatible = "aspeed,ast2600-scu-ic1";
+					reg = <0x570 0x4>;
+					interrupt-parent = <&gic>;
+					interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+					interrupt-controller;
+				};
 			};
 
 			rng: hwrng@...e2524 {
-- 
1.8.3.1