linux-kernel - Re: [PATCH 2/3] clk: let init callback return an error code

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Message-ID: <20190924161939.GD28770@lunn.ch>
Date:   Tue, 24 Sep 2019 18:19:39 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Jerome Brunet <jbrunet@...libre.com>
Cc:     Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, Heiko Stuebner <heiko@...ech.de>,
        Tero Kristo <t-kristo@...com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Heiner Kallweit <hkallweit1@...il.com>,
        "David S. Miller" <davem@...emloft.net>, netdev@...r.kernel.org,
        linux-amlogic@...ts.infradead.org, linux-arm-msm@...r.kernel.org,
        linux-rockchip@...ts.infradead.org, linux-omap@...r.kernel.org
Subject: Re: [PATCH 2/3] clk: let init callback return an error code

On Tue, Sep 24, 2019 at 02:39:53PM +0200, Jerome Brunet wrote:
> If the init callback is allowed to request resources, it needs a return
> value to report the outcome of such a request.
> 
> Signed-off-by: Jerome Brunet <jbrunet@...libre.com>
> ---
> 
>  Sorry about the spam.
>  This patch change quite a few files so I have tried to Cc the
>  relevant people. Stephen, You may notice that I have added a
>  couple of the network people. You need an Ack from one of them
>  since the Amlogic G12a mdio mux has a clock which uses the .init()
>  callback

>  static void __init of_ti_clockdomain_setup(struct device_node *node)
> diff --git a/drivers/net/phy/mdio-mux-meson-g12a.c b/drivers/net/phy/mdio-mux-meson-g12a.c
> index 7a9ad54582e1..bf86c9c7a288 100644
> --- a/drivers/net/phy/mdio-mux-meson-g12a.c
> +++ b/drivers/net/phy/mdio-mux-meson-g12a.c
> @@ -123,7 +123,7 @@ static int g12a_ephy_pll_is_enabled(struct clk_hw *hw)
>  	return (val & PLL_CTL0_LOCK_DIG) ? 1 : 0;
>  }
>  
> -static void g12a_ephy_pll_init(struct clk_hw *hw)
> +static int g12a_ephy_pll_init(struct clk_hw *hw)
>  {
>  	struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
>  
> @@ -136,6 +136,8 @@ static void g12a_ephy_pll_init(struct clk_hw *hw)
>  	writel(0x20200000, pll->base + ETH_PLL_CTL5);
>  	writel(0x0000c002, pll->base + ETH_PLL_CTL6);
>  	writel(0x00000023, pll->base + ETH_PLL_CTL7);
> +
> +	return 0;
>  }

Reviewed-by: Andrew Lunn <andrew@...n.ch>

It should be safe to merge this via the clk tree. You would probably
know about an possible merge conflicts, since you wrote this driver!

    Andrew