linux-kernel - [PATCH v1 5/5] platform/x86: Add Atom based Elkhart Lake(EHL) platform support to intel_pmc

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Message-Id: <20190926192603.18647-6-gayatri.kammela@intel.com>
Date:   Thu, 26 Sep 2019 12:26:03 -0700
From:   Gayatri Kammela <gayatri.kammela@...el.com>
To:     platform-driver-x86@...r.kernel.org
Cc:     vishwanath.somayaji@...el.com, dvhart@...radead.org,
        linux-kernel@...r.kernel.org, charles.d.prestopine@...el.com,
        Gayatri Kammela <gayatri.kammela@...el.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Srinivas Pandruvada <srinivas.pandruvada@...el.com>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        Kan Liang <kan.liang@...el.com>,
        "David E . Box" <david.e.box@...el.com>,
        Rajneesh Bhardwaj <rajneesh.bhardwaj@...el.com>,
        Tony Luck <tony.luck@...el.com>
Subject: [PATCH v1 5/5] platform/x86: Add Atom based Elkhart Lake(EHL) platform support to intel_pmc_core driver

Add Elkhart Lake to the list of the platforms that intel_pmc_core
driver supports for pmc_core device.

Just like ICL and TGL, EHL can also reuse all the CNL PCH IPs. Also, it
uses the same PCH IPs of TGL, no additional effort is needed to enable
but to simply reuse them.

Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Srinivas Pandruvada <srinivas.pandruvada@...el.com>
Cc: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Cc: Kan Liang <kan.liang@...el.com>
Cc: David E. Box <david.e.box@...el.com>
Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@...el.com>
Cc: Tony Luck <tony.luck@...el.com>
Reviewed-by: Tony Luck <tony.luck@...el.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@...el.com>
---
 drivers/platform/x86/intel_pmc_core.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index aef8f6d8bddb..2047b54fad54 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -190,7 +190,10 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
 	{"SDX",                 BIT(4)},
 	{"SPE",                 BIT(5)},
 	{"Fuse",                BIT(6)},
-	/* Reserved for Cannonlake but valid for Icelake and Tigerlake */
+	/*
+	 * Reserved for Cannonlake but valid for Icelake,
+	 * Tigerlake and Elkhart lake.
+	 */
 	{"SBR8",		BIT(7)},
 
 	{"CSME_FSC",            BIT(0)},
@@ -234,7 +237,10 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
 	{"HDA_PGD4",            BIT(2)},
 	{"HDA_PGD5",            BIT(3)},
 	{"HDA_PGD6",            BIT(4)},
-	/* Reserved for Cannonlake but valid for Icelake and Tigerlake */
+	/*
+	 * Reserved for Cannonlake but valid for Icelake,
+	 * Tigerlake and Elkhart lake.
+	 */
 	{"PSF6",		BIT(5)},
 	{"PSF7",		BIT(6)},
 	{"PSF8",		BIT(7)},
@@ -266,7 +272,7 @@ static const struct pmc_bit_map *ext_icl_pfear_map[] = {
 };
 
 static const struct pmc_bit_map tgl_pfear_map[] = {
-	/* Tigerlake generation onwards only */
+	/* Tigerlake and Elkhart lake generation onwards only */
 	{"PSF9",		BIT(0)},
 	{"RES_66",		BIT(1)},
 	{"RES_67",		BIT(2)},
@@ -872,6 +878,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
 	INTEL_CPU_FAM6(ICELAKE_NNPI, icl_reg_map),
 	INTEL_CPU_FAM6(TIGERLAKE_L, tgl_reg_map),
 	INTEL_CPU_FAM6(TIGERLAKE, tgl_reg_map),
+	INTEL_CPU_FAM6(ATOM_TREMONT, tgl_reg_map),
 	{}
 };
 
-- 
2.17.1