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Message-ID: <CAHp75VfwpYLVn2qWBMK11eR3D5VwnGf7VeYE=cQfq_y78ct75A@mail.gmail.com>
Date:   Fri, 27 Sep 2019 09:06:04 +0300
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     Gayatri Kammela <gayatri.kammela@...el.com>
Cc:     Platform Driver <platform-driver-x86@...r.kernel.org>,
        Vishwanath Somayaji <vishwanath.somayaji@...el.com>,
        Darren Hart <dvhart@...radead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        charles.d.prestopine@...el.com,
        Peter Zijlstra <peterz@...radead.org>,
        Srinivas Pandruvada <srinivas.pandruvada@...el.com>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        Kan Liang <kan.liang@...el.com>,
        "David E . Box" <david.e.box@...el.com>,
        Rajneesh Bhardwaj <rajneesh.bhardwaj@...el.com>,
        Tony Luck <tony.luck@...el.com>
Subject: Re: [PATCH v1 0/5] Add Tiger Lake/Elkhart Lake support to pmc_core driver

On Fri, Sep 27, 2019 at 9:01 AM Andy Shevchenko
<andy.shevchenko@...il.com> wrote:
> On Thu, Sep 26, 2019 at 9:43 PM Gayatri Kammela
> <gayatri.kammela@...el.com> wrote:
>
> Thank you for the series, I'll comment them later.
>
> For now, check how to properly setup prefix for all patches. The Title
> all broken.
>

On top of that the fully inconsistent SoC naming through the existing
code / new additions.

I'm pretty sure you need to spell platforms as Tiger Lake, Elkhart
Lake and so on everywhere.

Fix this, but do not send new version till I look at the code here.

> > Patch 1: Cleans up termination lines
> > Patch 2: Refactor driver for ease of adding new SoCs
> > Patch 3: Refactor debugfs entry for PCH IPs power gating status
> > Patch 4: Add Tiger Lake legacy support to pmc_core
> > Patch 5: Add Elkhart Lake legacy support to pmc_core
> >
> > All the information regarding the PCH IPs and names of IPs will be available
> > in *future* Intel's Platform Controller Hub (PCH) External Design Specification
> > (EDS) document.
>
> When?

-- 
With Best Regards,
Andy Shevchenko

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