[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <0473526e-df0a-94a5-5c22-debd0084ab16@ti.com>
Date: Fri, 27 Sep 2019 16:47:46 +0300
From: Tomi Valkeinen <tomi.valkeinen@...com>
To: Adam Ford <aford173@...il.com>
CC: Tony Lindgren <tony@...mide.com>, Tero Kristo <t-kristo@...com>,
Linux-OMAP <linux-omap@...r.kernel.org>,
Adam Ford <adam.ford@...icpd.com>,
BenoƮt Cousson <bcousson@...libre.com>,
dri-devel <dri-devel@...ts.freedesktop.org>,
devicetree <devicetree@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] drm/omap: Migrate minimum FCK/PCK ratio from Kconfig to
dts
On 27/09/2019 15:33, Adam Ford wrote:
>> It looks like a bug in omap clock handling.
>>
>> DSS uses dss1_alwon_fck_3430es2 as fclk. dss1_alwon_fck_3430es2 comes
>> from dpll4_ck, and there's a divider after the PLL, dpll4_m4_ck.
>>
>> When the DSS driver sets dss1_alwon_fck_3430es2 rate to 27000000 or
>> 27870967, which can be created with m4 dividers 32 and 31, it looks like
>> the divider goes to bypass, or to a very small value. DSS gets a very
>> high clock rate and breaks down.
>
> Is there anything I can do to help troubleshoot this? I could insert
> a hack that checks if we're omap3 and if so make the divider equal to
> 4, but that seems like just a hack.
> I can run more tests or insert code somewhere if you want.
I think it's up to someone who's knowledgeable in omap clock framework.
I'm kind of hoping that Tero or Tony would be willing to debug =). I can
try to find time to debug the omap clk framework, but I'll be going on
blindly there.
Tomi
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
Powered by blists - more mailing lists