linux-kernel - [PATCH] x86/cpufeatures: Add feature bit RDPRU on AMD

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-ID: <20191007204839.5727.10803.stgit@localhost.localdomain>
Date:   Mon, 07 Oct 2019 15:48:39 -0500
From:   Babu Moger <babu.moger@....com>
To:     tglx@...utronix.de, mingo@...hat.com, bp@...en8.de, hpa@...or.com,
        x86@...nel.org
Cc:     fenghua.yu@...el.com, jpoimboe@...hat.com, aaronlewis@...gle.com,
        robert.hu@...ux.intel.com, ak@...ux.intel.com,
        thellstrom@...are.com, linux-kernel@...r.kernel.org
Subject: [PATCH] x86/cpufeatures: Add feature bit RDPRU on AMD

AMD Zen 2 introduces new RDPRU instruction which is used to give access
to some processor registers that are typically only accessible when the
privilege level is zero.

ECX is used as the implicit register to specify which register to read.
RDPRU places the specified register’s value into EDX:EAX

For example, RDPRU instruction can be used to reading MPERF and APERF at
user level.

Adding this to cpu feature definition, so it is visible in /proc/cpuinfo.

Details are available in AMD64 Architecture Programmer’s Manual.
https://www.amd.com/system/files/TechDocs/24594.pdf

Signed-off-by: Babu Moger <babu.moger@....com>
---
 arch/x86/include/asm/cpufeatures.h |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 0652d3e..5d2f1a7 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -292,6 +292,7 @@
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
 #define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */
 #define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */
+#define X86_FEATURE_RDPRU		(13*32+ 4) /* read processor register at user level */
 #define X86_FEATURE_WBNOINVD		(13*32+ 9) /* WBNOINVD instruction */
 #define X86_FEATURE_AMD_IBPB		(13*32+12) /* "" Indirect Branch Prediction Barrier */
 #define X86_FEATURE_AMD_IBRS		(13*32+14) /* "" Indirect Branch Restricted Speculation */