lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20191007124443.00006082@huawei.com>
Date:   Mon, 7 Oct 2019 12:44:43 +0100
From:   Jonathan Cameron <jonathan.cameron@...wei.com>
To:     Miquel Raynal <miquel.raynal@...tlin.com>
CC:     Jonathan Cameron <jic23@...nel.org>,
        Hartmut Knaack <knaack.h@....de>,
        Lars-Peter Clausen <lars@...afoo.de>,
        Peter Meerwald-Stadler <pmeerw@...erw.net>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        <devicetree@...r.kernel.org>, <linux-iio@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        "Thomas Petazzoni" <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH v2 2/7] iio: adc: max1027: Make it optional to use
 interrupts

On Mon, 7 Oct 2019 12:01:22 +0200
Miquel Raynal <miquel.raynal@...tlin.com> wrote:

> Hi Jonathan,
> 
> Jonathan Cameron <jic23@...nel.org> wrote on Sun, 6 Oct 2019 11:18:37
> +0100:
> 
> > On Thu,  3 Oct 2019 19:33:56 +0200
> > Miquel Raynal <miquel.raynal@...tlin.com> wrote:
> >   
> > > The chip has a 'start conversion' and a 'end of conversion' pair of
> > > pins. They can be used but this is absolutely not mandatory as regular
> > > polling of the value is totally fine with the current internal
> > > clocking setup. Turn the interrupts optional and do not error out if
> > > they are not inquired in the device tree. This has the effect to
> > > prevent triggered buffers use though.
> > > 
> > > Signed-off-by: Miquel Raynal <miquel.raynal@...tlin.com>    
> > 
> > Hmm. I haven't looked a this in a great deal of depth but if we support
> > single channel reads it should be possible to allow the use of a
> > trigger from elsewhere.  Looks like a fair bit of new code would be needed
> > to support that though.  So perhaps this is a good first step.
> > 
> > It's a bit annoying that the hardware doesn't provide a EOC bit
> > anywhere in the registers.  That would have allowed us to be a bit
> > cleverer.  
> 
> I totally agree. Actually, this chip does not support any 'register
> read', the only things we can read are measures (temperature/voltages).

Ah. Good point.  Shall we polled reading of channels which is what
I meant ;)

Jonathan

> 
> 
> Thanks,
> Miquèl


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ