linux-kernel - Re: [PATCH v2] rtc: Fix the AltCentury value on AMD/Hygon platform

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20191008094419.GT4254@piout.net>
Date:   Tue, 8 Oct 2019 11:44:19 +0200
From:   Alexandre Belloni <alexandre.belloni@...tlin.com>
To:     Jinke Fan <fanjinke@...on.cn>
Cc:     a.zummo@...ertech.it, puwen@...on.cn, thomas.lendacky@....com,
        kim.phillips@....com, linux-rtc@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] rtc: Fix the AltCentury value on AMD/Hygon platform

On 08/10/2019 17:37:12+0800, Jinke Fan wrote:
> When using following operations:
> date -s "21190910 19:20:00"
> hwclock -w
> to change date from 2019 to 2119 for test, it will fail on Hygon
> Dhyana and AMD Zen CPUs, while the same operations run ok on Intel i7
> platform.
> 
> MC146818 driver use function mc146818_set_time() to set register
> RTC_FREQ_SELECT(RTC_REG_A)'s bit4-bit6 field which means divider stage
> reset value on Intel platform to 0x7.
> 
> While AMD/Hygon RTC_REG_A(0Ah)'s bit4 is defined as DV0 [Reference]:
> DV0 = 0 selects Bank 0, DV0 = 1 selects Bank 1. Bit5-bit6 is defined
> as reserved.
> 
> DV0 is set to 1, it will select Bank 1, which will disable AltCentury
> register(0x32) access. As UEFI pass acpi_gbl_FADT.century 0x32
> (AltCentury), the CMOS write will be failed on code:
> CMOS_WRITE(century, acpi_gbl_FADT.century).
> 
> Correct RTC_REG_A bank select bit(DV0) to 0 on AMD/Hygon CPUs, it will
> enable AltCentury(0x32) register writing and finally setup century as
> expected.
> 
> Test results on AMD/Hygon machine show that it works as expected.
> 
> Reference:
> https://www.amd.com/system/files/TechDocs/51192_Bolton_FCH_RRG.pdf
> section: 3.13 Real Time Clock (RTC)
> 
> Reported-by: kbuild test robot <lkp@...el.com>
> Signed-off-by: Jinke Fan <fanjinke@...on.cn>
> ---
>  drivers/rtc/rtc-mc146818-lib.c | 9 +++++++--
>  include/linux/mc146818rtc.h    | 6 ++++++
>  2 files changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/rtc/rtc-mc146818-lib.c b/drivers/rtc/rtc-mc146818-lib.c
> index 2ecd8752b088..a821dbe215d3 100644
> --- a/drivers/rtc/rtc-mc146818-lib.c
> +++ b/drivers/rtc/rtc-mc146818-lib.c
> @@ -170,9 +170,14 @@ int mc146818_set_time(struct rtc_time *time)
>  	}
>  
>  	save_control = CMOS_READ(RTC_CONTROL);
> -	CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
> +	CMOS_WRITE((save_control | RTC_SET), RTC_CONTROL);

Unrelated change.

>  	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
> -	CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
> +
> +#if defined(CONFIG_CPU_SUP_AMD) || defined(CONFIG_CPU_SUP_HYGON)
> +	CMOS_WRITE((save_freq_select & (~RTC_DV0)), RTC_FREQ_SELECT);

That does break all the other x86 platforms.

> +#else
> +	CMOS_WRITE((save_freq_select | RTC_DIV_RESET2), RTC_FREQ_SELECT);
> +#endif
>  
>  #ifdef CONFIG_MACH_DECSTATION
>  	CMOS_WRITE(real_yrs, RTC_DEC_YEAR);
> diff --git a/include/linux/mc146818rtc.h b/include/linux/mc146818rtc.h
> index 0661af17a758..590ac7849c78 100644
> --- a/include/linux/mc146818rtc.h
> +++ b/include/linux/mc146818rtc.h
> @@ -86,6 +86,12 @@ struct cmos_rtc_board_info {
>     /* 2 values for divider stage reset, others for "testing purposes only" */
>  #  define RTC_DIV_RESET1	0x60
>  #  define RTC_DIV_RESET2	0x70
> +
> +#if defined(CONFIG_CPU_SUP_AMD) || defined(CONFIG_CPU_SUP_HYGON)
> +   /* DV0 = 0 selects Bank 0, DV0 = 1 selects Bank 1 on AMD/Hygon platform */
> +#  define RTC_DV0		0x10
> +#endif
> +
>    /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
>  # define RTC_RATE_SELECT 	0x0F
>  
> -- 
> 2.17.1
> 

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com