linux-kernel - Re: [PATCH RFC 3/3] mtd: rawnand: Add support Macronix power down mode

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Message-ID: <OF7A229151.50591C54-ON48258495.00249AAF-48258495.002612F1@mxic.com.tw>
Date:   Wed, 16 Oct 2019 14:55:52 +0800
From:   masonccyang@...c.com.tw
To:     "Miquel Raynal" <miquel.raynal@...tlin.com>
Cc:     bbrezillon@...nel.org,
        "Boris Brezillon" <boris.brezillon@...labora.com>,
        computersforpeace@...il.com, dwmw2@...radead.org,
        frieder.schrempf@...tron.de, gregkh@...uxfoundation.org,
        juliensu@...c.com.tw, linux-kernel@...r.kernel.org,
        linux-mtd@...ts.infradead.org, marcel.ziswiler@...adex.com,
        marek.vasut@...il.com, richard@....at, tglx@...utronix.de,
        vigneshr@...com
Subject: Re: [PATCH RFC 3/3] mtd: rawnand: Add support Macronix power down mode

Hi Miquel,

> > 
> > > > > > +   nand_select_target(chip, 0); 
> > > > > 
> > > > > On several NAND controllers there is no way to act on the CS 
line
> > > > > without actually writing bytes to the NAND chip. So basically 
this
> > > > > is very likely to not work. 
> > > > 
> > > > any other way to make it work ? GPIO ?
> > > > or just have some comments description here.
> > > > i.e,.
> > > > 
> > > > /* The NAND chip will exit the deep power down mode with #CS 
toggling, 
> > 
> > > >  * please refer to datasheet for the timing requirement of tCRDP 
and 
> > tRDP.
> > > >  */
> > > > 
> > > 
> > > Good luck with that. As Miquel said, on most NAND controllers
> > > select_target() is a dummy operation that just assigns 
nand_chip->target
> > > to the specified value but doesn't assert the CS line. You could 
send a
> > > dummy command here, like a READ_ID, but I guess you need CS to be
> > > asserted for at least 20ns before asserting any other signals 
(CLE/ALE)
> > > which might be an issue. 
> > 
> > okay, got it.
> > But if possible, I think adding CS line control in 
nand_select_target()
> > is a simple and generic way for MTD and all raw NAND controllers.
> 
> The problem is not that we do not want to; the problem is that
> controllers are not capable of doing it reliably if no byte is sent
> over the NAND bus.

okay,  it's kind of pity even though our raw NAND controller is capable of 

doing it with no byte is sent over the NAND bus.

As you mentioned that other controllers are not capable of doing it 
reliably 
if no byte is sent over the NAND bus.
if so, does it work by adding a NAND_OP_DUMMY_INSTR ? (as Boris's 
comments)

thanks for your time & comments.

Mason

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