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Message-ID: <9216886d-62d4-db9f-8397-20f77c07ee76@ti.com>
Date:   Wed, 23 Oct 2019 15:32:29 +0300
From:   Jyri Sarha <jsarha@...com>
To:     Roger Quadros <rogerq@...com>, <kishon@...com>
CC:     <aniljoy@...ence.com>, <adouglas@...ence.com>, <nsekhar@...com>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>
Subject: Re: [PATCH v2 0/3] phy: cadence: j721e-wiz: Add Type-C plug flip
 support

On 23/10/2019 11:49, Roger Quadros wrote:
> Hi,
> 
> On J721e platform, the 2 lanes of SERDES PHY are used to achieve
> USB Type-C plug flip support without any additional MUX component
> by using a lane swap feature.
> 
> However, the driver needs to know the Type-C plug orientation before
> it can decide whether to swap the lanes or not. This is achieved via a
> GPIO named DIR.
> 
> Another constraint is that the lane swap must happen only when the PHY
> is in inactive state. This is achieved by sampling the GPIO and
> programming the lane swap before bringing the PHY out of reset.
> 
> This series adds support to read the GPIO and accordingly program
> the Lane swap for Type-C plug flip support.
> 
> Series must be applied on top of
> https://lkml.org/lkml/2019/10/16/517
> 
> cheers,
> -roger
> 
> Changelog:
> v2
> - revise commit log of patch 1
> - use regmap_field in patch 3
> 

Reviewed-by: Jyri Sarha <jsarha@...com>

For the whole series.

> Roger Quadros (3):
>   phy: cadence: Sierra: add phy_reset hook
>   dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO
>   phy: ti: j721e-wiz: Manage typec-gpio-dir
> 
>  .../bindings/phy/ti,phy-j721e-wiz.txt         |  9 ++++
>  drivers/phy/cadence/phy-cadence-sierra.c      | 10 ++++
>  drivers/phy/ti/phy-j721e-wiz.c                | 48 +++++++++++++++++++
>  3 files changed, 67 insertions(+)
> 


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