linux-kernel - Re: [PATCH v2 2/3] dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO

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Message-ID: <d8398dc4-cd6c-a3d1-1951-f1ad3d1b3ae3@ti.com>
Date:   Wed, 23 Oct 2019 18:30:26 +0530
From:   Kishon Vijay Abraham I <kishon@...com>
To:     Roger Quadros <rogerq@...com>
CC:     <aniljoy@...ence.com>, <adouglas@...ence.com>, <nsekhar@...com>,
        <jsarha@...com>, <linux-kernel@...r.kernel.org>,
        <devicetree@...r.kernel.org>
Subject: Re: [PATCH v2 2/3] dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir
 GPIO

Roger,

On 23/10/19 2:19 PM, Roger Quadros wrote:
> This is an optional GPIO, if specified will be used to
> swap lane 0 and lane 1 based on GPIO status. This is required
> to achieve plug flip support for USB Type-C.
> 
> Type-C companions typically need some time after the cable is
> plugged before and before they reflect the correct status of
> Type-C plug orientation on the DIR line.
> 
> Type-C Spec specifies CC attachment debounce time (tCCDebounce)
> of 100 ms (min) to 200 ms (max).
> 
> Allow the DT node to specify the time (in ms) that we need
> to wait before sampling the DIR line.
> 
> Signed-off-by: Roger Quadros <rogerq@...com>
> Signed-off-by: Sekhar Nori <nsekhar@...com>
> ---
>  .../devicetree/bindings/phy/ti,phy-j721e-wiz.txt         | 9 +++++++++

I've posted new version to change the binding document to YAML format. Can you
make the changes on top of that series?

Thanks
Kishon

>  1 file changed, 9 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt
> index 19b4c3e855d6..253535a8819f 100644
> --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt
> +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt
> @@ -24,6 +24,15 @@ Optional properties:
>  assigned-clocks and assigned-clock-parents: As documented in the generic
>  clock bindings in Documentation/devicetree/bindings/clock/clock-bindings.txt
>  
> + - typec-dir-gpios: GPIO to signal Type-C cable orientation for lane swap.
> +     If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
> +     achieve the funtionality of an exernal type-C plug flip mux.
> +
> + - typec-dir-debounce: Number of milliseconds to wait before sampling
> +     typec-dir-gpio. If not specified, the GPIO will be sampled ASAP.
> +     Type-C spec states minimum CC pin debounce of 100 ms and maximum
> +     of 200 ms.
> +
>  Required subnodes:
>   - Clock Subnode: WIZ node should have '3' subnodes for each of the clock
>       selects it supports. The clock subnodes should have the following names
>