linux-kernel - Re: [PATCHv2 0/3] Add LLCC support for SC7180 SoC

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Message-ID: <CAL_Jsq+5p7gQzDfGipNFr1ry-Pc3pDJpcXnAqdX9eo0HLETATQ@mail.gmail.com>
Date:   Thu, 24 Oct 2019 17:33:04 -0500
From:   Rob Herring <robh+dt@...nel.org>
To:     Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
Cc:     Bjorn Andersson <bjorn.andersson@...aro.org>,
        Mark Rutland <mark.rutland@....com>,
        devicetree@...r.kernel.org, Andy Gross <agross@...nel.org>,
        Stephen Boyd <swboyd@...omium.org>,
        linux-arm-msm <linux-arm-msm@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        Rishabh Bhatnagar <rishabhb@...eaurora.org>,
        Doug Anderson <dianders@...omium.org>,
        linux-arm-msm-owner@...r.kernel.org
Subject: Re: [PATCHv2 0/3] Add LLCC support for SC7180 SoC

On Thu, Oct 24, 2019 at 6:00 AM Sai Prakash Ranjan
<saiprakash.ranjan@...eaurora.org> wrote:
>
> Hi Rob,
>
> On 2019-10-24 01:19, Rob Herring wrote:
> > On Sun, Oct 20, 2019 at 10:32 PM Bjorn Andersson
> > <bjorn.andersson@...aro.org> wrote:
> >>
> >> On Sat 19 Oct 04:37 PDT 2019, Sai Prakash Ranjan wrote:
> >>
> >> > LLCC behaviour is controlled by the configuration data set
> >> > in the llcc-qcom driver, add the same for SC7180 SoC.
> >> > Also convert the existing bindings to json-schema and add
> >> > the compatible for SC7180 SoC.
> >> >
> >>
> >> Thanks for the patches and thanks for the review Stephen. Series
> >> applied
> >
> > And they break dt_binding_check. Please fix.
> >
>
> I did check this and think that the error log from dt_binding_check is
> not valid because it says cache-level is a required property [1], but
> there is no such property in LLCC bindings.

Then you should point out the issue and not just submit stuff ignoring
it. It has to be resolved one way or another.

If you refer to the DT spec[1], cache-level is required. The schema is
just enforcing that now. It's keying off the node name of
'cache-controller'.

Rob

[1] https://github.com/devicetree-org/devicetree-specification/blob/master/source/devicenodes.rst#multi-level-and-shared-cache-nodes-cpuscpul-cache