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Date:   Fri, 25 Oct 2019 08:53:19 -0700 (PDT)
From:   Paul Walmsley <paul.walmsley@...ive.com>
To:     Yash Shah <yash.shah@...ive.com>
cc:     "Paul Walmsley ( Sifive)" <paul.walmsley@...ifive.com>,
        "Palmer Dabbelt ( Sifive)" <palmer@...ifive.com>,
        "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "aou@...s.berkeley.edu" <aou@...s.berkeley.edu>,
        "will@...nel.org" <will@...nel.org>,
        "catalin.marinas@....com" <catalin.marinas@....com>,
        "allison@...utok.net" <allison@...utok.net>,
        "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "Anup.Patel@....com" <Anup.Patel@....com>,
        "rppt@...ux.ibm.com" <rppt@...ux.ibm.com>,
        Greentime Hu <greentime.hu@...ifive.com>,
        "alex@...ti.fr" <alex@...ti.fr>,
        "logang@...tatee.com" <logang@...tatee.com>,
        "sorear2@...il.com" <sorear2@...il.com>,
        Sachin Ghadi <sachin.ghadi@...ive.com>
Subject: Re: [PATCH v2] RISC-V: Add PCIe I/O BAR memory mapping

On Fri, 25 Oct 2019, Yash Shah wrote:

> For legacy I/O BARs (non-MMIO BARs) to work correctly on RISC-V Linux,
> we need to establish a reserved memory region for them, so that drivers
> that wish to use the legacy I/O BARs can issue reads and writes against
> a memory region that is mapped to the host PCIe controller's I/O BAR
> mapping.
> 
> Signed-off-by: Yash Shah <yash.shah@...ive.com>

Thanks.  And just to confirm: this is a fix, right?  Without this patch, 
legacy PCIe I/O resources won't be accessible on RISC-V?


- Paul

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