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Date:   Fri, 1 Nov 2019 16:07:01 +0100
From:   Maxime Ripard <mripard@...nel.org>
To:     Ondrej Jirman <megous@...ous.com>
Cc:     linux-sunxi@...glegroups.com, Yangtao Li <tiny.windzz@...il.com>,
        "Rafael J. Wysocki" <rjw@...ysocki.net>,
        Viresh Kumar <viresh.kumar@...aro.org>,
        Chen-Yu Tsai <wens@...e.org>,
        "open list:ALLWINNER CPUFREQ DRIVER" <linux-pm@...r.kernel.org>,
        "moderated list:ARM/Allwinner sunXi SoC support" 
        <linux-arm-kernel@...ts.infradead.org>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] cpufreq: sun50i: Fix CPU speed bin detection

On Thu, Oct 31, 2019 at 07:13:58PM +0100, Ondrej Jirman wrote:
> I have failures to boot on Orange Pi 3, because this driver determined
> that my SoC is from the normal bin, but my SoC only works reliably with
> the OPP values for the slowest bin.
>
> Looking at BSP code, I found that efuse values have following meanings
> on H6:
>
> - 0b000 invalid (interpreted in vendor's BSP as normal bin)
> - 0b001 slowest bin
> - 0b011 normal bin
> - 0b111 fastest bin
>
> Let's play it safe and interpret 0 as the slowest bin, but fix detection
> of other bins to match vendor code.
>
> Fixes: f328584f7bff ("cpufreq: Add sun50i nvmem based CPU scaling driver")
> Signed-off-by: Ondrej Jirman <megous@...ous.com>

Acked-by: Maxime Ripard <mripard@...nel.org>

Out of curiosity, which OPP table is being used? I guess it's one of
the dozens of patches sitting there...

Maxime

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