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Date:   Wed, 6 Nov 2019 22:38:13 +0530
From:   Vinod Koul <vkoul@...nel.org>
To:     Radhey Shyam Pandey <radhey.shyam.pandey@...inx.com>
Cc:     robh+dt@...nel.org, mark.rutland@....com, dan.j.williams@...el.com,
        michal.simek@...inx.com, anirudha.sarangi@...inx.com,
        nick.graumann@...il.com, andrea.merello@...il.com,
        appana.durga.rao@...inx.com, mcgrof@...nel.org,
        dmaengine@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org
Subject: Re: [PATCH -next 0/6] dmaengine: xilinx_dma: Add Xilinx AXI MCDMA
 Engine driver support

On 22-10-19, 22:30, Radhey Shyam Pandey wrote:
> This patchset adds Xilinx AXI MCDMA IP support. The AXI MCDMA provides
> high-bandwidth direct memory access between memory and AXI4-Stream target
> peripherals. It supports up to 16 independent read/write channels.
> 
> MCDMA IP supports per channel interrupt output but driver support one
> interrupt per channel for simplification. IP specification/programming
> sequence and register description is mentioned in PG [1].
> 
> The driver is tested with xilinx internal dmatest client. In end usecase
> MCDMA will be used by xilinx axiethernet driver using dma API's.

Applied, thanks

-- 
~Vinod

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