linux-kernel - Re: [PATCH v4 02/14] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc

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Message-ID: <5dc4588e.1c69fb81.5f75c.83ad@mx.google.com>
Date:   Thu, 07 Nov 2019 09:46:53 -0800
From:   Stephen Boyd <swboyd@...omium.org>
To:     Rajendra Nayak <rnayak@...eaurora.org>, agross@...nel.org,
        bjorn.andersson@...aro.org, robh+dt@...nel.org
Cc:     linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, mka@...omium.org,
        Rajendra Nayak <rnayak@...eaurora.org>,
        Taniya Das <tdas@...eaurora.org>
Subject: Re: [PATCH v4 02/14] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc

Quoting Rajendra Nayak (2019-11-05 22:50:05)
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> new file mode 100644
> index 000000000000..17870dd67390
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -0,0 +1,299 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * SC7180 SoC device tree source
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <dt-bindings/clock/qcom,gcc-sc7180.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +       interrupt-parent = <&intc>;
> +
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +
> +       chosen { };
> +
> +       clocks {
> +               xo_board: xo-board {
> +                       compatible = "fixed-clock";
> +                       clock-frequency = <38400000>;
> +                       #clock-cells = <0>;
> +               };
> +
> +               sleep_clk: sleep-clk {
> +                       compatible = "fixed-clock";
> +                       clock-frequency = <32764>;
> +                       clock-output-names = "sleep_clk";

Remove this one too?

> +                       #clock-cells = <0>;
> +               };
> +       };
> +
[...]
> +       memory@...00000 {
> +               device_type = "memory";
> +               /* We expect the bootloader to fill in the size */
> +               reg = <0 0x80000000 0 0>;
> +       };
> +
> +       pmu {
> +               compatible = "arm,armv8-pmuv3";
> +               interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       psci {
> +               compatible = "arm,psci-1.0";
> +               method = "smc";
> +       };
> +
> +       soc: soc {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges = <0 0 0 0 0x10 0>;
> +               dma-ranges = <0 0 0 0 0x10 0>;
> +               compatible = "simple-bus";
> +
> +               gcc: clock-controller@...000 {
> +                       compatible = "qcom,gcc-sc7180";
> +                       reg = <0 0x00100000 0 0x1f0000>;
> +                       #clock-cells = <1>;
> +                       #reset-cells = <1>;
> +                       #power-domain-cells = <1>;
> +               };
> +
> +               qupv3_id_1: geniqup@...000 {
> +                       compatible = "qcom,geni-se-qup";
> +                       reg = <0 0x00ac0000 0 0x6000>;
> +                       clock-names = "m-ahb", "s-ahb";
> +                       clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> +                                <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +                       status = "disabled";
> +
> +                       uart8: serial@...000 {
> +                               compatible = "qcom,geni-debug-uart";
> +                               reg = <0 0x00a88000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart8_default>;
> +                               interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> +                               status = "disabled";
> +                       };
> +               };
> +
> +               tlmm: pinctrl@...0000 {
> +                       compatible = "qcom,sc7180-pinctrl";
> +                       reg = <0 0x03500000 0 0x300000>,
> +                             <0 0x03900000 0 0x300000>,
> +                             <0 0x03d00000 0 0x300000>;
> +                       reg-names = "west", "north", "south";
> +                       interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +                       gpio-controller;
> +                       #gpio-cells = <2>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +                       gpio-ranges = <&tlmm 0 0 120>;
> +
> +                       qup_uart8_default: qup-uart8-default {
> +                               pinmux {
> +                                       pins = "gpio44", "gpio45";
> +                                       function = "qup12";

That looks weird to have qup12 function on uart8. It's right?

> +                               };
> +                       };
> +               };
> +