lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <5790f59f-951a-f1b4-bb31-f9cefec0c642@codeaurora.org>
Date:   Fri, 8 Nov 2019 09:18:57 +0530
From:   Rajendra Nayak <rnayak@...eaurora.org>
To:     Stephen Boyd <swboyd@...omium.org>, agross@...nel.org,
        bjorn.andersson@...aro.org, robh+dt@...nel.org
Cc:     linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, mka@...omium.org,
        Taniya Das <tdas@...eaurora.org>
Subject: Re: [PATCH v4 02/14] arm64: dts: sc7180: Add minimal dts/dtsi files
 for SC7180 soc



On 11/7/2019 11:16 PM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2019-11-05 22:50:05)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> new file mode 100644
>> index 000000000000..17870dd67390
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> @@ -0,0 +1,299 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * SC7180 SoC device tree source
>> + *
>> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/clock/qcom,gcc-sc7180.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> +       interrupt-parent = <&intc>;
>> +
>> +       #address-cells = <2>;
>> +       #size-cells = <2>;
>> +
>> +       chosen { };
>> +
>> +       clocks {
>> +               xo_board: xo-board {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <38400000>;
>> +                       #clock-cells = <0>;
>> +               };
>> +
>> +               sleep_clk: sleep-clk {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <32764>;
>> +                       clock-output-names = "sleep_clk";
> 
> Remove this one too?

ah, yes. Not sure how I missed that :/

> 
>> +                       #clock-cells = <0>;
>> +               };
>> +       };
>> +
> [...]
>> +       memory@...00000 {
>> +               device_type = "memory";
>> +               /* We expect the bootloader to fill in the size */
>> +               reg = <0 0x80000000 0 0>;
>> +       };
>> +
>> +       pmu {
>> +               compatible = "arm,armv8-pmuv3";
>> +               interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
>> +       };
>> +
>> +       psci {
>> +               compatible = "arm,psci-1.0";
>> +               method = "smc";
>> +       };
>> +
>> +       soc: soc {
>> +               #address-cells = <2>;
>> +               #size-cells = <2>;
>> +               ranges = <0 0 0 0 0x10 0>;
>> +               dma-ranges = <0 0 0 0 0x10 0>;
>> +               compatible = "simple-bus";
>> +
>> +               gcc: clock-controller@...000 {
>> +                       compatible = "qcom,gcc-sc7180";
>> +                       reg = <0 0x00100000 0 0x1f0000>;
>> +                       #clock-cells = <1>;
>> +                       #reset-cells = <1>;
>> +                       #power-domain-cells = <1>;
>> +               };
>> +
>> +               qupv3_id_1: geniqup@...000 {
>> +                       compatible = "qcom,geni-se-qup";
>> +                       reg = <0 0x00ac0000 0 0x6000>;
>> +                       clock-names = "m-ahb", "s-ahb";
>> +                       clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
>> +                                <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
>> +                       #address-cells = <2>;
>> +                       #size-cells = <2>;
>> +                       ranges;
>> +                       status = "disabled";
>> +
>> +                       uart8: serial@...000 {
>> +                               compatible = "qcom,geni-debug-uart";
>> +                               reg = <0 0x00a88000 0 0x4000>;
>> +                               clock-names = "se";
>> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
>> +                               pinctrl-names = "default";
>> +                               pinctrl-0 = <&qup_uart8_default>;
>> +                               interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
>> +                               status = "disabled";
>> +                       };
>> +               };
>> +
>> +               tlmm: pinctrl@...0000 {
>> +                       compatible = "qcom,sc7180-pinctrl";
>> +                       reg = <0 0x03500000 0 0x300000>,
>> +                             <0 0x03900000 0 0x300000>,
>> +                             <0 0x03d00000 0 0x300000>;
>> +                       reg-names = "west", "north", "south";
>> +                       interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> +                       gpio-controller;
>> +                       #gpio-cells = <2>;
>> +                       interrupt-controller;
>> +                       #interrupt-cells = <2>;
>> +                       gpio-ranges = <&tlmm 0 0 120>;
>> +
>> +                       qup_uart8_default: qup-uart8-default {
>> +                               pinmux {
>> +                                       pins = "gpio44", "gpio45";
>> +                                       function = "qup12";
> 
> That looks weird to have qup12 function on uart8. It's right?

So we have 2 qup instances each with 6 SEs on sc7180.
So the i2c/uart/spi SE instances are numbered from 0 to 5 in the first qup
and 6 to 11 in the next.
The pinctrl functions however have it named qup0 to 5 for first and
qup10 to 15 for the next which is weird. Now all data in the pinctrl
driver is autogenerated using hw description so its coming from that.

Just for comparison, on sdm845 we had 2 qup instances with 8 SE's
and the function names were qup0 to 8 for first and 9 to 15 for the
second.

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ