lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Fri, 08 Nov 2019 13:20:14 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     Sowjanya Komatineni <skomatineni@...dia.com>, jason@...edaemon.net,
        jonathanh@...dia.com, linus.walleij@...aro.org,
        marc.zyngier@....com, mark.rutland@....com, stefan@...er.ch,
        tglx@...utronix.de, thierry.reding@...il.com
Cc:     pdeschrijver@...dia.com, pgaikwad@...dia.com,
        linux-clk@...r.kernel.org, linux-gpio@...r.kernel.org,
        jckuo@...dia.com, josephl@...dia.com, talho@...dia.com,
        skomatineni@...dia.com, linux-tegra@...r.kernel.org,
        linux-kernel@...r.kernel.org, mperttunen@...dia.com,
        spatra@...dia.com, robh+dt@...nel.org, digetx@...il.com,
        devicetree@...r.kernel.org, rjw@...ysocki.net,
        viresh.kumar@...aro.org, linux-pm@...r.kernel.org
Subject: Re: [PATCH v9 11/22] clk: tegra: clk-dfll: Add suspend and resume support

Quoting Sowjanya Komatineni (2019-08-16 12:41:56)
> diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
> index f8688c2ddf1a..c051d92c2bbf 100644
> --- a/drivers/clk/tegra/clk-dfll.c
> +++ b/drivers/clk/tegra/clk-dfll.c
> @@ -1487,6 +1487,7 @@ static int dfll_init(struct tegra_dfll *td)
>         td->last_unrounded_rate = 0;
>  
>         pm_runtime_enable(td->dev);
> +       pm_runtime_irq_safe(td->dev);

Why irq_safe? It would be good to mention it in the commit text or
something.

>         pm_runtime_get_sync(td->dev);
>  
>         dfll_set_mode(td, DFLL_DISABLED);
> @@ -1513,6 +1514,61 @@ static int dfll_init(struct tegra_dfll *td)
>         return ret;
>  }
>  
> +/**
> + * tegra_dfll_suspend - check DFLL is disabled
> + * @dev: DFLL device *
> + *
> + * DFLL clock should be disabled by the CPUFreq driver. So, make
> + * sure it is disabled and disable all clocks needed by the DFLL.
> + */
> +int tegra_dfll_suspend(struct device *dev)
> +{
> +       struct tegra_dfll *td = dev_get_drvdata(dev);
> +
> +       if (dfll_is_running(td)) {
> +               dev_err(td->dev, "DFLL still enabled while suspending\n");
> +               return -EBUSY;
> +       }
> +
> +       reset_control_assert(td->dvco_rst);
> +
> +       return 0;
> +}
> +EXPORT_SYMBOL(tegra_dfll_suspend);
> +
> +/**
> + * tegra_dfll_resume - reinitialize DFLL on resume
> + * @dev: DFLL instance

I prefer this description for tegra_dfll_suspend's 'dev' argument.

> + *
> + * DFLL is disabled and reset during suspend and resume.
> + * So, reinitialize the DFLL IP block back for use.
> + * DFLL clock is enabled later in closed loop mode by CPUFreq
> + * driver before switching its clock source to DFLL output.
> + */
> +int tegra_dfll_resume(struct device *dev)
> +{
> +       struct tegra_dfll *td = dev_get_drvdata(dev);
> +
> +       reset_control_deassert(td->dvco_rst);
> +
> +       pm_runtime_get_sync(td->dev);
> +
> +       dfll_set_mode(td, DFLL_DISABLED);
> +       dfll_set_default_params(td);

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ