linux-kernel - Re: [PATCH v8 2/3] dwc: PCI: intel: PCIe RC controller driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 20 Nov 2019 15:08:26 +0200
From:   Andy Shevchenko <andriy.shevchenko@...el.com>
To:     Dilip Kota <eswara.kota@...ux.intel.com>
Cc:     gustavo.pimentel@...opsys.com, lorenzo.pieralisi@....com,
        andrew.murray@....com, helgaas@...nel.org, jingoohan1@...il.com,
        robh@...nel.org, martin.blumenstingl@...glemail.com,
        linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, cheol.yong.kim@...el.com,
        chuanhua.lei@...ux.intel.com, qi-ming.wu@...el.com
Subject: Re: [PATCH v8 2/3] dwc: PCI: intel: PCIe RC controller driver

On Wed, Nov 20, 2019 at 03:43:01PM +0800, Dilip Kota wrote:
> Add support to PCIe RC controller on Intel Gateway SoCs.
> PCIe controller is based of Synopsys DesignWare PCIe core.
> 
> Intel PCIe driver requires Upconfigure support, Fast Training
> Sequence and link speed configurations. So adding the respective
> helper functions in the PCIe DesignWare framework.
> It also programs hardware autonomous speed during speed
> configuration so defining it in pci_regs.h.

> +static void pcie_app_wr_mask(struct intel_pcie_port *lpp,
> +			     u32 ofs, u32 mask, u32 val)

It seems your editor is misconfigured. First line should be

static void pcie_app_wr_mask(struct intel_pcie_port *lpp, u32 ofs,

in case you would like to split it logically.

> +static void pcie_rc_cfg_wr_mask(struct intel_pcie_port *lpp,
> +				u32 ofs, u32 mask, u32 val)

Ditto.

> +	pcie_app_wr(lpp,  PCIE_APP_IRNCR, PCIE_APP_IRN_INT);

Extra white space.

-- 
With Best Regards,
Andy Shevchenko