linux-kernel - RE: [PATCH v4 4/5] scsi: ufs: Do not clear the DL layer timers

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Message-ID: <MN2PR04MB6991FAA95F79EFB1EE030D13FC4A0@MN2PR04MB6991.namprd04.prod.outlook.com>
Date:   Mon, 25 Nov 2019 07:22:35 +0000
From:   Avri Altman <Avri.Altman@....com>
To:     Can Guo <cang@...eaurora.org>,
        "asutoshd@...eaurora.org" <asutoshd@...eaurora.org>,
        "nguyenb@...eaurora.org" <nguyenb@...eaurora.org>,
        "rnayak@...eaurora.org" <rnayak@...eaurora.org>,
        "linux-scsi@...r.kernel.org" <linux-scsi@...r.kernel.org>,
        "kernel-team@...roid.com" <kernel-team@...roid.com>,
        "saravanak@...gle.com" <saravanak@...gle.com>,
        "salyzyn@...gle.com" <salyzyn@...gle.com>
CC:     Alim Akhtar <alim.akhtar@...sung.com>,
        Pedro Sousa <pedrom.sousa@...opsys.com>,
        "James E.J. Bottomley" <jejb@...ux.ibm.com>,
        "Martin K. Petersen" <martin.petersen@...cle.com>,
        Stanley Chu <stanley.chu@...iatek.com>,
        Bean Huo <beanhuo@...ron.com>,
        Tomas Winkler <tomas.winkler@...el.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Allison Randal <allison@...utok.net>,
        open list <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v4 4/5] scsi: ufs: Do not clear the DL layer timers

> >
> > During power mode change, PACP_PWR_Req frame sends
> PAPowerModeUserData
> > parameters (and they are considered valid by device if Flags[4] -
> > UserDataValid bit is set in the same frame).
> > Currently we don't set these PAPowerModeUserData parameters and
> > hardware always sets UserDataValid bit which would clear all the DL
> > layer timeout values of the peer device after the power mode change.
> >
> > This change sets the PAPowerModeUserData[0..5] to UniPro specification
> > recommended default values, in addition we are also setting the
> > relevant
> > DME_LOCAL_* timer attributes as required by UFS HCI specification.
> >
> > Signed-off-by: Can Guo <cang@...eaurora.org>
> Reviewed-by Avri Altman <avri.altman@....com>
BTW, I noticed that you are only updating the TC0 registers.
Why not setting the TC1 registers as well?

Thanks,
Avri