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Message-ID: <1575358332-44866-1-git-send-email-xingyu.chen@amlogic.com>
Date: Tue, 3 Dec 2019 15:32:12 +0800
From: Xingyu Chen <xingyu.chen@...ogic.com>
To: Kevin Hilman <khilman@...libre.com>,
Neil Armstrong <narmstrong@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>
CC: Xingyu Chen <xingyu.chen@...ogic.com>,
Rob Herring <robh+dt@...nel.org>,
Jonathan Cameron <jic23@...nel.org>,
Jerome Brunet <jbrunet@...libre.com>,
Qianggui Song <qianggui.song@...ogic.com>,
Jianxin Pan <jianxin.pan@...ogic.com>,
Jian Hu <jian.hu@...ogic.com>, <linux-iio@...r.kernel.org>,
<linux-amlogic@...ts.infradead.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>
Subject: [PATCH] arm64: dts: a1: add saradc controller
The saradc controller in Meson-A1 is the same as the Meson-G12 series SoCs,
so we use the same compatible string.
Signed-off-by: Xingyu Chen <xingyu.chen@...ogic.com>
---
This patch is based on A1 clock patchset at [0].
[0] https://lore.kernel.org/linux-amlogic/20191129144605.182774-1-jian.hu@amlogic.com
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..cad1756 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -93,6 +93,21 @@
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+ saradc: adc@...0 {
+ compatible = "amlogic,meson-g12a-saradc",
+ "amlogic,meson-saradc";
+ reg = <0x0 0x2c00 0x0 0x48>;
+ #io-channel-cells = <1>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>,
+ <&clkc_periphs CLKID_SARADC>,
+ <&clkc_periphs CLKID_SARADC_CLK>,
+ <&clkc_periphs CLKID_SARADC_SEL>;
+ clock-names = "clkin", "core", "adc_clk",
+ "adc_sel";
+ status = "disabled";
+ };
};
gic: interrupt-controller@...01000 {
--
2.7.4
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