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Message-ID: <7hpngxqfa7.fsf@baylibre.com>
Date: Mon, 09 Dec 2019 14:56:32 -0800
From: Kevin Hilman <khilman@...libre.com>
To: Xingyu Chen <xingyu.chen@...ogic.com>,
Neil Armstrong <narmstrong@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc: Xingyu Chen <xingyu.chen@...ogic.com>,
Rob Herring <robh+dt@...nel.org>,
Jonathan Cameron <jic23@...nel.org>,
Jerome Brunet <jbrunet@...libre.com>,
Qianggui Song <qianggui.song@...ogic.com>,
Jianxin Pan <jianxin.pan@...ogic.com>,
Jian Hu <jian.hu@...ogic.com>, linux-iio@...r.kernel.org,
linux-amlogic@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: a1: add saradc controller
Xingyu Chen <xingyu.chen@...ogic.com> writes:
> The saradc controller in Meson-A1 is the same as the Meson-G12 series SoCs,
> so we use the same compatible string.
>
> Signed-off-by: Xingyu Chen <xingyu.chen@...ogic.com>
>
> ---
> This patch is based on A1 clock patchset at [0].
>
> [0] https://lore.kernel.org/linux-amlogic/20191129144605.182774-1-jian.hu@amlogic.com
> ---
> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> index 7210ad0..cad1756 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> @@ -93,6 +93,21 @@
> clock-names = "xtal", "pclk", "baud";
> status = "disabled";
> };
> +
> + saradc: adc@...0 {
> + compatible = "amlogic,meson-g12a-saradc",
> + "amlogic,meson-saradc";
> + reg = <0x0 0x2c00 0x0 0x48>;
Why 0x48 here? AXG uses 0x38 and you're not adding any more registers
to this driver.
Kevin
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