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Message-ID: <CAHp75Vf7d=Gw24MTq2q3BKspkLEDDM24GVK4Zh_4zfZEzVuZjw@mail.gmail.com>
Date: Tue, 3 Dec 2019 21:27:30 +0200
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: Andrew Murray <andrew.murray@....com>
Cc: Srinath Mannam <srinath.mannam@...adcom.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Florian Fainelli <f.fainelli@...il.com>,
Ray Jui <rjui@...adcom.com>, Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Arnd Bergmann <arnd@...db.de>,
bcm-kernel-feedback-list <bcm-kernel-feedback-list@...adcom.com>,
linux-pci@...r.kernel.org, devicetree <devicetree@...r.kernel.org>,
linux-arm Mailing List <linux-arm-kernel@...ts.infradead.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Ray Jui <ray.jui@...adcom.com>
Subject: Re: [PATCH v3 2/6] PCI: iproc: Add INTx support with better modeling
On Tue, Dec 3, 2019 at 5:55 PM Andrew Murray <andrew.murray@....com> wrote:
> On Tue, Dec 03, 2019 at 10:27:02AM +0530, Srinath Mannam wrote:
> > + /* go through INTx A, B, C, D until all interrupts are handled */
> > + do {
> > + status = iproc_pcie_read_reg(pcie, IPROC_PCIE_INTX_CSR);
>
> By performing this read once and outside of the do/while loop you may improve
> performance. I wonder how probable it is to get another INTx whilst handling
> one?
May I ask how it can be improved?
One read will be needed any way, and so does this code.
> > + for_each_set_bit(bit, &status, PCI_NUM_INTX) {
> > + virq = irq_find_mapping(pcie->irq_domain, bit);
> > + if (virq)
> > + generic_handle_irq(virq);
> > + else
> > + dev_err(dev, "unexpected INTx%u\n", bit);
> > + }
> > + } while ((status & SYS_RC_INTX_MASK) != 0);
--
With Best Regards,
Andy Shevchenko
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