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Message-ID: <8a7709b6-215c-939a-906d-0ed7c3c2dbd8@ti.com>
Date: Fri, 6 Dec 2019 15:02:10 +0530
From: Vignesh Raghavendra <vigneshr@...com>
To: Ashish Kumar <ashish.kumar@....com>,
Tudor Ambarus <tudor.ambarus@...rochip.com>
CC: Miquel Raynal <miquel.raynal@...tlin.com>,
Richard Weinberger <richard@....at>,
"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
John Garry <john.garry@...wei.com>
Subject: Re: [EXT] [PATCH 1/3] mtd: spi-nor: Split mt25qu512a (n25q512a) entry
into two
On 12/5/2019 12:54 PM, Ashish Kumar wrote:
> Hi Vignesh,
[...]
>> drivers/mtd/spi-nor/spi-nor.c | 9 +++++----
>> 1 file changed, 5 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
>> index f4afe123e9dc..01efea022990 100644
>> --- a/drivers/mtd/spi-nor/spi-nor.c
>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>> @@ -2459,15 +2459,16 @@ static const struct flash_info spi_nor_ids[] = {
>> { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
>> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K |
>> SPI_NOR_QUAD_READ) },
>> { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR |
>> SPI_NOR_QUAD_READ) },
>> + { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
>> + SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
>> + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> It seems you have moved back to my original patch [1], wrt mt25qu512a.
>
Yes, it seems like n25q and mt25q are not really same... mt25q supports
stateless 4 byte addressing opcodes where as n25q does not. Hence we
cannot add SPI_NOR_4B_OPCODES to n25q's idcodes.
This patch is outcome of from U-Boot discussion here (I believe you were
cc'd as well):
https://patchwork.ozlabs.org/patch/1160501/
Regards
Vignesh
> Regards
> Ashish
>> + { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
>> + SPI_NOR_QUAD_READ) },
>> { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR |
>> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>> { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR |
>> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>> { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096,
>> SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
>> NO_CHIP_ERASE) },
>> - { "mt25qu512a (n25q512a)", INFO(0x20bb20, 0, 64 * 1024, 1024,
>> - SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
>> - SPI_NOR_QUAD_READ |
>> - SPI_NOR_4B_OPCODES) },
>> { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR |
>> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>>
>> /* Micron */
>> --
>> 2.24.0
> [1]: http://patchwork.ozlabs.org/patch/1146197/
>
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