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Message-ID: <20191206103505.GM18399@e119886-lin.cambridge.arm.com>
Date: Fri, 6 Dec 2019 10:35:05 +0000
From: Andrew Murray <andrew.murray@....com>
To: Eric Auger <eric.auger@...hat.com>
Cc: eric.auger.pro@...il.com, maz@...nel.org,
linux-kernel@...r.kernel.org, kvmarm@...ts.cs.columbia.edu,
james.morse@....com, suzuki.poulose@....com, drjones@...hat.com
Subject: Re: [RFC 1/3] KVM: arm64: pmu: Don't increment SW_INCR if PMCR.E is
unset
On Wed, Dec 04, 2019 at 09:44:24PM +0100, Eric Auger wrote:
> The specification says PMSWINC increments PMEVCNTR<n>_EL1 by 1
> if PMEVCNTR<n>_EL0 is enabled and configured to count SW_INCR.
>
> For PMEVCNTR<n>_EL0 to be enabled, we need both PMCNTENSET to
> be set for the corresponding event counter but we also need
> the PMCR.E bit to be set.
>
> Fixes: 7a0adc7064b8 ("arm64: KVM: Add access handler for PMSWINC register")
> Signed-off-by: Eric Auger <eric.auger@...hat.com>
> ---
> virt/kvm/arm/pmu.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
> index 8731dfeced8b..c3f8b059881e 100644
> --- a/virt/kvm/arm/pmu.c
> +++ b/virt/kvm/arm/pmu.c
> @@ -486,6 +486,9 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val)
> if (val == 0)
> return;
>
> + if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E))
> + return;
> +
Reviewed-by: Andrew Murray <andrew.murray@....com>
> enable = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
> for (i = 0; i < ARMV8_PMU_CYCLE_IDX; i++) {
> if (!(val & BIT(i)))
> --
> 2.20.1
>
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