[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <3e974fa60d0b5371e93fce86b23f686d@www.loen.fr>
Date: Mon, 09 Dec 2019 15:55:03 +0000
From: Marc Zyngier <maz@...nel.org>
To: Qais Yousef <qais.yousef@....com>
Cc: Hannes Reinecke <hare@...e.de>, John Garry <john.garry@...wei.com>,
Ming Lei <ming.lei@...hat.com>, <tglx@...utronix.de>,
<chenxiang66@...ilicon.com>, <bigeasy@...utronix.de>,
<linux-kernel@...r.kernel.org>, <hare@...e.com>, <hch@....de>,
<axboe@...nel.dk>, <bvanassche@....org>, <peterz@...radead.org>,
<mingo@...hat.com>
Subject: Re: [PATCH RFC 1/1] genirq: Make threaded handler use irq affinity for managed interrupt
On 2019-12-09 15:49, Qais Yousef wrote:
> On 12/09/19 15:17, Marc Zyngier wrote:
>> On 2019-12-09 15:09, Hannes Reinecke wrote:
>>
>> [slight digression]
>>
>> > My idea here is slightly different: can't we leverage SMT?
>> > Most modern CPUs do SMT (I guess even ARM does it nowadays)
>> > (Yes, I know about spectre and things. We're talking performance
>> here
>> > :-)
>>
>> I only know two of those: Cavium TX2 and ARM Neoverse-E1.
>
> There's the Cortex-A65 too.
Which is the exact same core as E1 (but don't tell anyone... ;-).
M.
--
Jazz is not dead. It just smells funny...
Powered by blists - more mailing lists