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Message-ID: <20191209010031.GP3365@dragon>
Date: Mon, 9 Dec 2019 09:05:55 +0800
From: Shawn Guo <shawnguo@...nel.org>
To: Abel Vesa <abel.vesa@....com>
Cc: Aisheng Dong <aisheng.dong@....com>,
Stephen Boyd <sboyd@...nel.org>,
Sascha Hauer <kernel@...gutronix.de>,
Jacky Bai <ping.bai@....com>,
Daniel Baluta <daniel.baluta@....com>,
dl-linux-imx <linux-imx@....com>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
"S.j. Wang" <shengjiu.wang@....com>
Subject: Re: [PATCH 1/3] dt-bindings: imx8-clock: Add ADMA clock ids
On Wed, Nov 13, 2019 at 12:25:13PM +0000, Abel Vesa wrote:
> According to the RM, the Audio and DMA (ADMA) subsystem is a collection
> of audio peripherals and some system modules.
> Add the ADMA specific clock ids to the dt-bindings clock file.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@....com>
> Signed-off-by: Abel Vesa <abel.vesa@....com>
> ---
> include/dt-bindings/clock/imx8-clock.h | 96 +++++++++++++++++++++++++++++++++-
> 1 file changed, 94 insertions(+), 2 deletions(-)
>
> diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h
> index 673a8c6..6e0c752 100644
> --- a/include/dt-bindings/clock/imx8-clock.h
> +++ b/include/dt-bindings/clock/imx8-clock.h
> @@ -131,7 +131,60 @@
> #define IMX_ADMA_PWM_CLK 188
> #define IMX_ADMA_LCD_CLK 189
>
> -#define IMX_SCU_CLK_END 190
> +#define IMX_ADMA_AUD_PLL0 190
> +#define IMX_ADMA_AUD_PLL1 191
> +
> +#define IMX_ADMA_AUD_PLL_DIV_CLK0_CLK 192
> +#define IMX_ADMA_AUD_PLL_DIV_CLK1_CLK 193
> +#define IMX_ADMA_AUD_REC_CLK0_CLK 194
> +#define IMX_ADMA_AUD_REC_CLK1_CLK 195
> +
> +/* CM40 SS */
> +#define IMX_CM40_IPG_CLK 196
> +#define IMX_CM40_I2C_DIV 197
These two don't look like ADMA clock.
Shawn
> +
> +#define IMX_SCU_CLK_END 198
> +
> +#define IMX_ADMA_ACM_AUD_CLK0_SEL 0
> +#define IMX_ADMA_ACM_AUD_CLK0_CLK 1
> +#define IMX_ADMA_ACM_AUD_CLK1_SEL 2
> +#define IMX_ADMA_ACM_AUD_CLK1_CLK 3
> +#define IMX_ADMA_ACM_MCLKOUT0_SEL 4
> +#define IMX_ADMA_ACM_MCLKOUT1_SEL 5
> +#define IMX_ADMA_ACM_ESAI0_MCLK_SEL 6
> +#define IMX_ADMA_ACM_GPT0_MUX_CLK_SEL 7
> +#define IMX_ADMA_ACM_GPT1_MUX_CLK_SEL 8
> +#define IMX_ADMA_ACM_GPT2_MUX_CLK_SEL 9
> +#define IMX_ADMA_ACM_GPT3_MUX_CLK_SEL 10
> +#define IMX_ADMA_ACM_GPT4_MUX_CLK_SEL 11
> +#define IMX_ADMA_ACM_GPT5_MUX_CLK_SEL 12
> +#define IMX_ADMA_ACM_SAI0_MCLK_SEL 13
> +#define IMX_ADMA_ACM_SAI1_MCLK_SEL 14
> +#define IMX_ADMA_ACM_SAI2_MCLK_SEL 15
> +#define IMX_ADMA_ACM_SAI3_MCLK_SEL 16
> +#define IMX_ADMA_ACM_SAI4_MCLK_SEL 17
> +#define IMX_ADMA_ACM_SAI5_MCLK_SEL 18
> +#define IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL 19
> +#define IMX_ADMA_ACM_MQS_TX_CLK_SEL 20
> +#define IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL 21
> +#define IMX_ADMA_ACM_ASRC1_MUX_CLK_SEL 22
> +
> +#define IMX_ADMA_EXT_AUD_MCLK0 23
> +#define IMX_ADMA_EXT_AUD_MCLK1 24
> +#define IMX_ADMA_ESAI0_RX_CLK 25
> +#define IMX_ADMA_ESAI0_RX_HF_CLK 26
> +#define IMX_ADMA_ESAI0_TX_CLK 27
> +#define IMX_ADMA_ESAI0_TX_HF_CLK 28
> +#define IMX_ADMA_SPDIF0_RX 29
> +#define IMX_ADMA_SAI0_RX_BCLK 30
> +#define IMX_ADMA_SAI0_TX_BCLK 31
> +#define IMX_ADMA_SAI1_RX_BCLK 32
> +#define IMX_ADMA_SAI1_TX_BCLK 33
> +#define IMX_ADMA_SAI2_RX_BCLK 34
> +#define IMX_ADMA_SAI3_RX_BCLK 35
> +#define IMX_ADMA_SAI4_RX_BCLK 36
> +
> +#define IMX_ADMA_ACM_CLK_END 37
>
> /* LPCG clocks */
>
> @@ -287,7 +340,46 @@
> #define IMX_ADMA_LPCG_DSP_IPG_CLK 42
> #define IMX_ADMA_LPCG_DSP_CORE_CLK 43
> #define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44
> +#define IMX_ADMA_LPCG_AMIX_IPG_CLK 45
> +#define IMX_ADMA_LPCG_ESAI_0_IPG_CLK 46
> +#define IMX_ADMA_LPCG_ESAI_0_EXTAL_CLK 47
> +#define IMX_ADMA_LPCG_SAI_0_IPG_CLK 48
> +#define IMX_ADMA_LPCG_SAI_0_MCLK 49
> +#define IMX_ADMA_LPCG_SAI_1_IPG_CLK 50
> +#define IMX_ADMA_LPCG_SAI_1_MCLK 51
> +#define IMX_ADMA_LPCG_SAI_2_IPG_CLK 52
> +#define IMX_ADMA_LPCG_SAI_2_MCLK 53
> +#define IMX_ADMA_LPCG_SAI_3_IPG_CLK 54
> +#define IMX_ADMA_LPCG_SAI_3_MCLK 55
> +#define IMX_ADMA_LPCG_SAI_4_IPG_CLK 56
> +#define IMX_ADMA_LPCG_SAI_4_MCLK 57
> +#define IMX_ADMA_LPCG_SAI_5_IPG_CLK 58
> +#define IMX_ADMA_LPCG_SAI_5_MCLK 59
> +#define IMX_ADMA_LPCG_MQS_IPG_CLK 60
> +#define IMX_ADMA_LPCG_MQS_MCLK 61
> +#define IMX_ADMA_LPCG_GPT5_IPG_CLK 62
> +#define IMX_ADMA_LPCG_GPT5_CLKIN 63
> +#define IMX_ADMA_LPCG_GPT6_IPG_CLK 64
> +#define IMX_ADMA_LPCG_GPT6_CLKIN 65
> +#define IMX_ADMA_LPCG_GPT7_IPG_CLK 66
> +#define IMX_ADMA_LPCG_GPT7_CLKIN 67
> +#define IMX_ADMA_LPCG_GPT8_IPG_CLK 68
> +#define IMX_ADMA_LPCG_GPT8_CLKIN 69
> +#define IMX_ADMA_LPCG_GPT9_IPG_CLK 70
> +#define IMX_ADMA_LPCG_GPT9_CLKIN 71
> +#define IMX_ADMA_LPCG_GPT10_IPG_CLK 72
> +#define IMX_ADMA_LPCG_GPT10_CLKIN 73
> +#define IMX_ADMA_LPCG_MCLKOUT0 74
> +#define IMX_ADMA_LPCG_MCLKOUT1 75
> +#define IMX_ADMA_LPCG_SPDIF_0_TX_CLK 76
> +#define IMX_ADMA_LPCG_SPDIF_0_GCLKW 77
> +#define IMX_ADMA_LPCG_ASRC_0_IPG_CLK 79
> +#define IMX_ADMA_LPCG_ASRC_1_IPG_CLK 80
> +#define IMX_ADMA_LPCG_AUD_PLL_DIV_CLK0_CLK 81
> +#define IMX_ADMA_LPCG_AUD_PLL_DIV_CLK1_CLK 82
> +#define IMX_ADMA_LPCG_AUD_REC_CLK0_CLK 83
> +#define IMX_ADMA_LPCG_AUD_REC_CLK1_CLK 84
>
> -#define IMX_ADMA_LPCG_CLK_END 45
> +#define IMX_ADMA_LPCG_CLK_END 85
>
> #endif /* __DT_BINDINGS_CLOCK_IMX_H */
> --
> 2.7.4
>
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