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Message-ID: <CAPDyKFo9Z2yj7zC5VOS-iX_LyavPp1A4n73eAp7VD-Q+dpoqpw@mail.gmail.com>
Date: Tue, 10 Dec 2019 10:51:22 +0100
From: Ulf Hansson <ulf.hansson@...aro.org>
To: Chaotian Jing <chaotian.jing@...iatek.com>
Cc: Matthias Brugger <matthias.bgg@...il.com>,
"linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
linux-mediatek@...ts.infradead.org,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
srv_heupstream <srv_heupstream@...iatek.com>, hsinyi@...gle.com
Subject: Re: [PATCH] mmc: mediatek: fix CMD_TA to 2 for MT8173 HS200/HS400 mode
On Wed, 4 Dec 2019 at 08:20, Chaotian Jing <chaotian.jing@...iatek.com> wrote:
>
> there is a chance that always get response CRC error after HS200 tuning,
> the reason is that need set CMD_TA to 2. this modification is only for
> MT8173.
>
> Signed-off-by: Chaotian Jing <chaotian.jing@...iatek.com>
I have applied this for fixes, however it seems like this should also
be tagged for stable, right?
Is there a specific commit this fixes or should we just find the
version it applies to?
Kind regards
Uffe
> ---
> drivers/mmc/host/mtk-sd.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> index 189e42674d85..010fe29a4888 100644
> --- a/drivers/mmc/host/mtk-sd.c
> +++ b/drivers/mmc/host/mtk-sd.c
> @@ -228,6 +228,7 @@
> #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
> #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
>
> +#define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */
> #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */
>
> #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
> @@ -1881,6 +1882,7 @@ static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
>
> /* select EMMC50 PAD CMD tune */
> sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
> + sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
>
> if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
> mmc->ios.timing == MMC_TIMING_UHS_SDR104)
> --
> 2.18.0
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