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Message-Id: <40bf8eb4-2998-43fd-af61-c9063b09ced9@www.fastmail.com>
Date: Wed, 11 Dec 2019 11:02:08 +1030
From: "Andrew Jeffery" <andrew@...id.au>
To: "Eddie James" <eajames@...ux.ibm.com>, linux-kernel@...r.kernel.org
Cc: devicetree@...r.kernel.org, "Jason Cooper" <jason@...edaemon.net>,
linux-aspeed@...ts.ozlabs.org, "Marc Zyngier" <maz@...nel.org>,
"Rob Herring" <robh+dt@...nel.org>, tglx@...utronix.de,
mark.rutland@....com, "Joel Stanley" <joel@....id.au>
Subject: Re: [PATCH v2 02/12] irqchip: Add Aspeed SCU interrupt controller
On Fri, 6 Dec 2019, at 03:45, Eddie James wrote:
> The Aspeed SOCs provide some interrupts through the System Control
> Unit registers. Add an interrupt controller that provides these
> interrupts to the system.
>
> Signed-off-by: Eddie James <eajames@...ux.ibm.com>
Reviewed-by: Andrew Jeffery <andrew@...id.au>
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