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Message-Id: <20191219052825.4146-1-vipulk0511@gmail.com>
Date: Thu, 19 Dec 2019 10:58:25 +0530
From: Vipul Kumar <vipulk0511@...il.com>
To: Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>
Cc: linux-kernel@...r.kernel.org, Stable <stable@...r.kernel.org>,
Cedric Hombourger <Cedric_Hombourger@...tor.com>,
Vipul Kumar <vipul_kumar@...tor.com>,
Srikanth Krishnakar <Srikanth_Krishnakar@...tor.com>,
Vipul Kumar <vipulk0511@...il.com>
Subject: [V2] x86/tsc: Unset TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Bay Trail SoC
From: Vipul Kumar <vipul_kumar@...tor.com>
'commit f3a02ecebed7 ("x86/tsc: Set TSC_KNOWN_FREQ and TSC_RELIABLE
flags on Intel Atom SoCs")', causing time drift for Bay trail SoC.
These flags are set for SoCs having cpuid_level 0x15 or more.
Bay trail is having cpuid_level 0xb.
So, unset both flags to make sure the clocksource calibration can
be done.
Signed-off-by: Vipul Kumar <vipul_kumar@...tor.com>
Cc: <stable@...r.kernel.org> # 4.14+
---
- Changes in v2:
- Added linux-stable along with kernel version in CC
---
arch/x86/kernel/tsc_msr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index e0cbe4f2af49..1ca27c28db98 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -112,6 +112,9 @@ unsigned long cpu_khz_from_msr(void)
lapic_timer_period = (freq * 1000) / HZ;
#endif
+ if (boot_cpu_data.cpuid_level < 0x15)
+ return res;
+
/*
* TSC frequency determined by MSR is always considered "known"
* because it is reported by HW.
--
2.20.1
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