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Message-Id: <20191219053244.88D3A222C2@mail.kernel.org>
Date:   Wed, 18 Dec 2019 21:32:43 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     Jeffrey Hugo <jeffrey.l.hugo@...il.com>,
        Taniya Das <tdas@...eaurora.org>
Cc:     Michael Turquette <mturquette@...libre.com>,
        David Brown <david.brown@...aro.org>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        MSM <linux-arm-msm@...r.kernel.org>, linux-soc@...r.kernel.org,
        linux-clk@...r.kernel.org, lkml <linux-kernel@...r.kernel.org>,
        DTML <devicetree@...r.kernel.org>, Rob Herring <robh@...nel.org>,
        Rob Herring <robh+dt@...nel.org>
Subject: Re: [PATCH v2 3/8] dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings

Quoting Taniya Das (2019-11-26 20:06:49)
> 
> 
> On 11/26/2019 11:41 PM, Stephen Boyd wrote:
> > Quoting Jeffrey Hugo (2019-11-15 07:11:01)
> >> On Fri, Nov 15, 2019 at 3:07 AM Taniya Das <tdas@...eaurora.org> wrote:
> >>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
> >>> new file mode 100644
> >>> index 0000000..c2d6243
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
> >>> +      - description: GPLL0 source from GCC
> >>
> >> This is not an accurate conversion.  GPLL0 was not valid for 845, and
> >> is required for 8998.
> > 
> > Thanks for checking Jeff.
> > 
> > It looks like on 845 there are two gpll0 clocks going to gpucc. From
> > gpu_cc_parent_map_0:
> > 
> >       "gcc_gpu_gpll0_clk_src",
> >       "gcc_gpu_gpll0_div_clk_src",
> > 
> 
> There are branches of GPLL0 which would be connected to most external 
> CCs. It is upto to the external CCs to either use them to source a 
> frequency or not.

Yes, they can decide to use them or not, but they really do go to the
CCs so the DT should describe that.

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