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Message-ID: <ccdb9e9163a37b25202412668a9cd4b4d1a51d16.camel@microchip.com>
Date: Fri, 20 Dec 2019 15:42:52 +0000
From: <Nicolas.Ferre@...rochip.com>
To: <Claudiu.Beznea@...rochip.com>, <sre@...nel.org>,
<alexandre.belloni@...tlin.com>
CC: <linux-arm-kernel@...ts.infradead.org>, <linux-pm@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 2/2] power: reset: at91-poweroff: use proper master
clock register offset
Le vendredi 20 décembre 2019 à 17:31 +0200, Claudiu Beznea a écrit :
> SAM9X60's PMC uses different offset for master clock register.
> Add a member of type struct pmc_reg_config in struct reg_config,
> fill it correspondingly for SAMA5D2 and SAM9X60 and use it in
> poweroff() function.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@...rochip.com>
> ---
> drivers/power/reset/at91-sama5d2_shdwc.c | 18 +++++++++++++++---
> 1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c
> b/drivers/power/reset/at91-sama5d2_shdwc.c
> index 84806d20846b..2fe3a627cb53 100644
> --- a/drivers/power/reset/at91-sama5d2_shdwc.c
> +++ b/drivers/power/reset/at91-sama5d2_shdwc.c
> @@ -74,8 +74,13 @@ struct shdwc_reg_config {
> u8 sr_rttwk_shift;
> };
>
> +struct pmc_reg_config {
> + u8 mckr;
> +};
> +
> struct reg_config {
> struct shdwc_reg_config shdwc;
> + struct pmc_reg_config pmc;
> };
>
> struct shdwc {
> @@ -136,9 +141,9 @@ static void at91_poweroff(void)
> " str %1, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
>
> /* Switch the master clock source to slow clock. */
> - "1: ldr r6, [%4, #" __stringify(AT91_PMC_MCKR)
> "]\n\t"
> + "1: ldr r6, [%4, %5]\n\t"
> " bic r6, r6, #" __stringify(AT91_PMC_CSS) "\n\t"
> - " str r6, [%4, #" __stringify(AT91_PMC_MCKR) "]\n\t"
> + " str r6, [%4, %5]\n\t"
> /* Wait for clock switch. */
> "2: ldr r6, [%4, #" __stringify(AT91_PMC_SR) "]\n\t"
> " tst r6, #" __stringify(AT91_PMC_MCKRDY) "\n\t"
> @@ -153,7 +158,8 @@ static void at91_poweroff(void)
> "r" cpu_to_le32(AT91_DDRSDRC_LPDDR2_PWOFF),
> "r" (at91_shdwc->shdwc_base),
> "r" cpu_to_le32(AT91_SHDW_KEY | AT91_SHDW_SHDW),
> - "r" (at91_shdwc->pmc_base)
> + "r" (at91_shdwc->pmc_base),
> + "r" (at91_shdwc->rcfg->pmc.mckr)
> : "r6");
> }
>
> @@ -253,6 +259,9 @@ static const struct reg_config sama5d2_reg_config = {
> .sr_rtcwk_shift = 5,
> .sr_rttwk_shift = SHDW_CFG_NOT_USED,
> },
> + .pmc = {
> + .mckr = 0x30,
> + },
> };
>
> static const struct reg_config sam9x60_reg_config = {
> @@ -263,6 +272,9 @@ static const struct reg_config sam9x60_reg_config = {
> .sr_rtcwk_shift = 5,
> .sr_rttwk_shift = 4,
> },
> + .pmc = {
> + .mckr = 0x28,
> + },
> };
>
> static const struct of_device_id at91_shdwc_of_match[] = {
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