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Message-ID: <CAHp75VfepiiVFLLmCwdBS0Z6tmR+XKBaOLg1qPPuz1McLjS=4Q@mail.gmail.com>
Date:   Mon, 13 Jan 2020 16:17:32 +0200
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     Mark Brown <broonie@...nel.org>
Cc:     John Garry <john.garry@...wei.com>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        tudor.ambarus@...rochip.com,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        chenxiang66@...ilicon.com, Linuxarm <linuxarm@...wei.com>,
        linux-spi <linux-spi@...r.kernel.org>,
        Marek Vasut <marek.vasut@...il.com>,
        "open list:MEMORY TECHNOLOGY..." <linux-mtd@...ts.infradead.org>,
        Jiancheng Xue <xuejiancheng@...ilicon.com>,
        fengsheng5@...wei.com,
        Mika Westerberg <mika.westerberg@...ux.intel.com>,
        wanghuiqiang <wanghuiqiang@...wei.com>, liusimin4@...wei.com
Subject: Re: [PATCH v2 2/3] spi: Add HiSilicon v3xx SPI NOR flash controller driver

On Mon, Jan 13, 2020 at 4:07 PM Mark Brown <broonie@...nel.org> wrote:
> On Mon, Jan 13, 2020 at 01:01:06PM +0000, John Garry wrote:
> > On 13/01/2020 11:42, Mark Brown wrote:
>
> > > The idiomatic approach appears to be for individual board vendors
> > > to allocate IDs, you do end up with multiple IDs from multiple
> > > vendors for the same thing.
>
> > But I am not sure how appropriate that same approach would be for some 3rd
> > party memory part which we're simply wiring up on our board. Maybe it is.
>
> It seems to be quite common for Intel reference designs to assign
> Intel IDs to non-Intel parts on the board (which is where I
> became aware of this practice).

Basically vendor of component in question is responsible for ID, but
it seems they simple don't care.

-- 
With Best Regards,
Andy Shevchenko

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