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Message-ID: <20200113162150.GO2838@lahna.fi.intel.com>
Date:   Mon, 13 Jan 2020 18:21:50 +0200
From:   Mika Westerberg <mika.westerberg@...ux.intel.com>
To:     Nicholas Johnson <nicholas.johnson-opensource@...look.com.au>
Cc:     Bjorn Helgaas <helgaas@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        Benjamin Herrenschmidt <benh@...nel.crashing.org>,
        Logan Gunthorpe <logang@...tatee.com>
Subject: Re: [PATCH v1 4/4] PCI: Allow extend_bridge_window() to shrink
 resource if necessary

On Wed, Jan 08, 2020 at 01:36:04AM +0000, Nicholas Johnson wrote:
> > Where's the patch that changes the caller so "new_size" may be smaller
> > than "size"?  I guess it must be "[3/3] PCI: Consider alignment of
> > hot-added bridges ..." because that's the only one that makes a
> > non-trivial change, right?
> 
> As above, there was always a possibility of the new_size being smaller. 
> For some reason, 1M is assigned to bridges, even if nothing is below 
> them (for example, unused non hotplug bridges in a Thunderbolt dock). It 
> may be an edge case if we are low on space, but theoretically it can 
> happen.
> 
> Also, when writing this, Mika was not interested in using hpmemsize, 
> which, when used, will cause new_size to be smaller than the current 
> size (actual size and add_size combined).

Just a small correction here about my motivation. So I'm testing on a
hardware where the BIOS assigns initial resources to the root/downstream
ports which is the majority of Thunderbolt capable PC systems nowadays.
Therefore the user does not need to pass any additional command line
parameters to get the ports working properly.

However, I'm of course interested in getting Linux PCI resource
management as good as possible regardless whether the firmware/BIOS
assigns them or not ;-)

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