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Message-ID: <20200114234110.GA24051@bogus>
Date: Tue, 14 Jan 2020 17:41:10 -0600
From: Rob Herring <robh@...nel.org>
To: Sandeep Maheswaram <sanm@...eaurora.org>
Cc: Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Kishon Vijay Abraham I <kishon@...com>,
Mark Rutland <mark.rutland@....com>,
Stephen Boyd <swboyd@...omium.org>,
Doug Anderson <dianders@...omium.org>,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, Manu Gautam <mgautam@...eaurora.org>
Subject: Re: [PATCH v2 3/3] dt-bindings: phy: qcom,qmp: Convert QMP phy
bindings to yaml
On Wed, Jan 08, 2020 at 05:59:41PM +0530, Sandeep Maheswaram wrote:
> Convert QMP phy bindings to DT schema format using json-schema.
>
> Signed-off-by: Sandeep Maheswaram <sanm@...eaurora.org>
> ---
> .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 201 ++++++++++++++++++
> .../devicetree/bindings/phy/qcom-qmp-phy.txt | 227 ---------------------
> 2 files changed, 201 insertions(+), 227 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> new file mode 100644
> index 0000000..6eb00f5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> @@ -0,0 +1,201 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Qualcomm QMP PHY controller
> +
> +maintainers:
> + - Manu Gautam <mgautam@...eaurora.org>
> +
> +description:
> + QMP phy controller supports physical layer functionality for a number of
> + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,ipq8074-qmp-pcie-phy
> + - qcom,ipq8074-qmp-pcie-phy
> + - qcom,msm8996-qmp-pcie-phy
> + - qcom,msm8996-qmp-usb3-phy
> + - qcom,msm8998-qmp-usb3-phy
> + - qcom,msm8998-qmp-ufs-phy
> + - qcom,msm8998-qmp-pcie-phy
> + - qcom,sc7180-qmp-usb3-phy
> + - qcom,sdm845-qmp-usb3-phy
> + - qcom,sdm845-qmp-usb3-uni-phy
> + - qcom,sdm845-qmp-ufs-phy
> + - qcom,sm8150-qmp-ufs-phy
> +
> + reg:
> + minItems: 1
> + items:
> + - description: Address and length of PHY's common serdes block.
> + - description: Address and length of the DP_COM control block.
> +
> + reg-names:
> + items:
> + - const: reg-base
> + - const: dp_com
> +
> + "#clock-cells":
> + enum: [ 1, 2 ]
> +
> + "#address-cells":
> + enum: [ 1, 2 ]
> +
> + "#size-cells":
> + enum: [ 1, 2 ]
> +
> + clocks:
> + anyOf:
Should be oneOf rather than anyOf. Did oneOf not work?
> + - items:
> + - description: Phy aux clock.
> + - description: Phy config clock.
> + - description: 19.2 MHz ref clk.
> + - description: Phy common block aux clock.
These should be indented 2 more spaces.
> + - items:
> + - description: Phy aux clock.
> + - description: Phy config clock.
> + - description: 19.2 MHz ref clk.
This can be dropped if you add 'minItems: 3' to the 1st case.
Then really, you should have an if/then to define which compatibles
require 4 items.
> + - items:
> + - description: 19.2 MHz ref clk.
> + - description: Phy reference aux clock.
> + - items:
> + - description: Phy reference aux clock.
> +
> + clock-names:
> + anyOf:
oneOf
> + - items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - const: com_aux
Indent 2 more...
> + - items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - items:
> + - const: ref
> + - const: ref_aux
> + - items:
> + - const: ref_aux
> +
> + resets:
> + anyOf:
oneOf
> + - items:
> + - description: reset of phy block.
> + - description: phy common block reset.
> + - description: ahb cfg block reset.
> + - items:
> + - description: reset of phy block.
> + - description: phy common block reset.
> + - items:
> + - description: ahb cfg block reset.
> + - description: PHY reset in the UFS controller.
> + - items:
> + - description: reset of phy block.
> + - items:
> + - description: PHY reset in the UFS controller.
> +
> + reset-names:
> + anyOf:
> + - items:
> + - const: phy
> + - const: common
> + - const: cfg
> + - items:
> + - const: phy
> + - const: common
> + - items:
> + - const: ahb
> + - const: ufsphy
> + - items:
> + - const: phy
> + - items:
> + - const: ufsphy
> +
> + vdda-phy-supply:
> + description:
> + Phandle to a regulator supply to PHY core block.
> +
> + vdda-pll-supply:
> + description:
> + Phandle to 1.8V regulator supply to PHY refclk pll block.
> +
> + vddp-ref-clk-supply:
> + description:
> + Phandle to a regulator supply to any specific refclk
> + pll block.
You need patternProperties with the child nodes defined.
> +
> +required:
> + - compatible
> + - reg
> + - "#clock-cells"
> + - "#address-cells"
> + - "#size-cells"
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - vdda-phy-supply
> + - vdda-pll-supply
Need a 'additionalProperties: false' here.
> +
> +if:
> + properties:
> + compatible:
> + contains:
> + anyOf:
> + - items:
> + - const: qcom,sdm845-qmp-usb3-phy
> + - items:
> + - const: qcom,sc7180-qmp-usb3-phy
> +then:
> + required:
> + - reg-names
> +
> +#Required nodes:
> +#Each device node of QMP phy is required to have as many child nodes as
> +#the number of lanes the PHY has.
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-sc7180.h>
> + usb_1_qmpphy: phy-wrapper@...9000 {
> + compatible = "qcom,sc7180-qmp-usb3-phy";
> + reg = <0 0x088e9000 0 0x18c>,
> + <0 0x088e8000 0 0x38>;
> + reg-names = "reg-base", "dp_com";
> + #clock-cells = <1>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> + <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> + clock-names = "aux", "cfg_ahb", "ref", "com_aux";
> +
> + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>;
> + reset-names = "phy";
> +
> + vdda-phy-supply = <&vreg_l3c_1p2>;
> + vdda-pll-supply = <&vreg_l4a_0p8>;
> +
> + usb_1_ssphy: phy@...9200 {
> + reg = <0 0x088e9200 0 0x128>,
> + <0 0x088e9400 0 0x200>,
> + <0 0x088e9c00 0 0x218>,
> + <0 0x088e9600 0 0x128>,
> + <0 0x088e9800 0 0x200>,
> + <0 0x088e9a00 0 0x18>;
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "usb3_phy_pipe_clk_src";
> + };
> + };
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