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Message-ID: <20200121170022.GA2665@lahna.fi.intel.com>
Date:   Tue, 21 Jan 2020 19:00:22 +0200
From:   Mika Westerberg <mika.westerberg@...ux.intel.com>
To:     Mark Brown <broonie@...nel.org>
Cc:     Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        Darren Hart <dvhart@...radead.org>,
        Lee Jones <lee.jones@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        "H . Peter Anvin" <hpa@...or.com>, x86@...nel.org,
        Zha Qipeng <qipeng.zha@...el.com>,
        "David E . Box" <david.e.box@...ux.intel.com>,
        Guenter Roeck <linux@...ck-us.net>,
        Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Wim Van Sebroeck <wim@...ux-watchdog.org>,
        platform-driver-x86@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 00/38] platform/x86: Rework intel_scu_ipc and
 intel_pmc_ipc drivers

On Tue, Jan 21, 2020 at 04:45:15PM +0000, Mark Brown wrote:
> On Tue, Jan 21, 2020 at 06:33:12PM +0200, Mika Westerberg wrote:
> 
> > Sorry about that. I included you because there was suggestion from Lee
> > to convert the MFD driver in patch 37 to use regmap but the registers
> > are all 64-bit and it was not clear whether regmap supports that:
> 
> >   https://www.spinics.net/lists/platform-driver-x86/msg20652.html
> 
> > Looking at the regmap API it seems to deal mostly with "unsigned int"
> > which does not work well with the 64-bit MMIO registers but I may be
> > missing something.
> 
> It should work fine on architectures with 64 bit ints but otherwise it's
> not supported (and doing so would hurt the API pretty badly so I'm not
> sure it would make sense but patches welcome).

OK, thanks for the clarification. I guess in this case we can probably
just live without using it, if that's fine for Lee and others. The new
MFD driver itself is ~500 lines so not sure how much regmap would help
there, and we only expose two simple functions for the subdevices both
dealing with 64-bit registers.

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