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Message-ID: <MN2PR04MB699108FC14777CC364522069FC070@MN2PR04MB6991.namprd04.prod.outlook.com>
Date: Fri, 31 Jan 2020 18:48:19 +0000
From: Avri Altman <Avri.Altman@....com>
To: Stanley Chu <stanley.chu@...iatek.com>,
"linux-scsi@...r.kernel.org" <linux-scsi@...r.kernel.org>,
"martin.petersen@...cle.com" <martin.petersen@...cle.com>,
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"beanhuo@...ron.com" <beanhuo@...ron.com>
CC: "asutoshd@...eaurora.org" <asutoshd@...eaurora.org>,
"cang@...eaurora.org" <cang@...eaurora.org>,
"matthias.bgg@...il.com" <matthias.bgg@...il.com>,
"bvanassche@....org" <bvanassche@....org>,
"linux-mediatek@...ts.infradead.org"
<linux-mediatek@...ts.infradead.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"kuohong.wang@...iatek.com" <kuohong.wang@...iatek.com>,
"peter.wang@...iatek.com" <peter.wang@...iatek.com>,
"chun-hung.wu@...iatek.com" <chun-hung.wu@...iatek.com>,
"andy.teng@...iatek.com" <andy.teng@...iatek.com>
Subject: RE: [PATCH RESEND v3 4/4] scsi: ufs-mediatek: gate ref-clk during
Auto-Hibern8
>
> +static u32 ufs_mtk_link_get_state(struct ufs_hba *hba)
> +{
> + u32 val;
> +
> + ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
> + val = ufshcd_readl(hba, REG_UFS_PROBE);
> + val = val >> 28;
> +
> + return val;
> +}
A little bit strange that you are relying on debug registers to setup your ref-clock.
Is this this debug info is always available?
Thanks,
Avri
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