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Message-ID: <1580521516.15794.10.camel@mtksdccf07>
Date: Sat, 1 Feb 2020 09:45:16 +0800
From: Stanley Chu <stanley.chu@...iatek.com>
To: Avri Altman <Avri.Altman@....com>
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Subject: RE: [PATCH RESEND v3 4/4] scsi: ufs-mediatek: gate ref-clk during
Auto-Hibern8
Hi Avri,
On Fri, 2020-01-31 at 18:48 +0000, Avri Altman wrote:
> >
> > +static u32 ufs_mtk_link_get_state(struct ufs_hba *hba)
> > +{
> > + u32 val;
> > +
> > + ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
> > + val = ufshcd_readl(hba, REG_UFS_PROBE);
> > + val = val >> 28;
> > +
> > + return val;
> > +}
> A little bit strange that you are relying on debug registers to setup your ref-clock.
> Is this this debug info is always available?
>
Yes, this register is only for this purpose now (query link state) and
always existed in MediaTek UFS host.
Thanks,
Stanley
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