linux-kernel - Re: [PATCH v3 3/9] drm/bridge: ti-sn65dsi86: Don't use MIPI variables for DP link

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Date:   Mon, 3 Feb 2020 15:33:11 -0800
From:   Bjorn Andersson <bjorn.andersson@...aro.org>
To:     Douglas Anderson <dianders@...omium.org>
Cc:     Andrzej Hajda <a.hajda@...sung.com>,
        Neil Armstrong <narmstrong@...libre.com>,
        robdclark@...omium.org, linux-arm-msm@...r.kernel.org,
        seanpaul@...omium.org, Jeffrey Hugo <jeffrey.l.hugo@...il.com>,
        Daniel Vetter <daniel@...ll.ch>,
        Rob Clark <robdclark@...il.com>,
        Jonas Karlman <jonas@...boo.se>, linux-kernel@...r.kernel.org,
        dri-devel@...ts.freedesktop.org, David Airlie <airlied@...ux.ie>,
        Jernej Skrabec <jernej.skrabec@...l.net>,
        Laurent Pinchart <Laurent.pinchart@...asonboard.com>
Subject: Re: [PATCH v3 3/9] drm/bridge: ti-sn65dsi86: Don't use MIPI
 variables for DP link

On Wed 18 Dec 14:35 PST 2019, Douglas Anderson wrote:

> The ti-sn65dsi86 is a bridge from MIPI to DP and thus has two links:
> the MIPI link and the DP link.  The two links do not need to have the
> same format or number of lanes.  Stop using MIPI variables when
> talking about the DP link.
> 
> This has zero functional change because:
> * currently we are hardcoding the MIPI link as unpacked RGB888 which
>   requires 24 bits and currently we are not changing the DP link rate
>   from the bridge's default of 8 bits per pixel.
> * currently we are hardcoding both the MIPI and DP as being 4 lanes.
> 
> This is all in prep for fixing some of the above.
> 
> Signed-off-by: Douglas Anderson <dianders@...omium.org>
> Tested-by: Rob Clark <robdclark@...il.com>
> Reviewed-by: Rob Clark <robdclark@...il.com>

Reviewed-by: Bjorn Andersson <bjorn.andersson@...aro.org>

> ---
> 
> Changes in v3: None
> Changes in v2: None
> 
>  drivers/gpu/drm/bridge/ti-sn65dsi86.c | 18 ++++++++++++------
>  1 file changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> index 7b596af265e4..ab644baaf90c 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -100,6 +100,7 @@ struct ti_sn_bridge {
>  	struct drm_panel		*panel;
>  	struct gpio_desc		*enable_gpio;
>  	struct regulator_bulk_data	supplies[SN_REGULATOR_SUPPLY_NUM];
> +	int				dp_lanes;
>  };
>  
>  static const struct regmap_range ti_sn_bridge_volatile_ranges[] = {
> @@ -313,6 +314,7 @@ static int ti_sn_bridge_attach(struct drm_bridge *bridge)
>  	}
>  
>  	/* TODO: setting to 4 lanes always for now */
> +	pdata->dp_lanes = 4;
>  	dsi->lanes = 4;
>  	dsi->format = MIPI_DSI_FMT_RGB888;
>  	dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
> @@ -451,13 +453,17 @@ static void ti_sn_bridge_set_dp_rate(struct ti_sn_bridge *pdata)
>  	struct drm_display_mode *mode =
>  		&pdata->bridge.encoder->crtc->state->adjusted_mode;
>  
> -	/* set DSIA clk frequency */
> -	bit_rate_mhz = (mode->clock / 1000) *
> -			mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
> +	/*
> +	 * Calculate minimum bit rate based on our pixel clock.  At
> +	 * the moment this driver never sets the DP_18BPP_EN bit in
> +	 * register 0x5b so we hardcode 24bpp.
> +	 */
> +	bit_rate_mhz = (mode->clock / 1000) * 24;
>  
> -	/* set DP data rate */
> -	dp_rate_mhz = ((bit_rate_mhz / pdata->dsi->lanes) * DP_CLK_FUDGE_NUM) /
> +	/* Calculate minimum DP data rate, taking 80% as per DP spec */
> +	dp_rate_mhz = ((bit_rate_mhz / pdata->dp_lanes) * DP_CLK_FUDGE_NUM) /
>  							DP_CLK_FUDGE_DEN;
> +
>  	for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
>  		if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz)
>  			break;
> @@ -517,7 +523,7 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge)
>  			   CHA_DSI_LANES_MASK, val);
>  
>  	/* DP lane config */
> -	val = DP_NUM_LANES(pdata->dsi->lanes - 1);
> +	val = DP_NUM_LANES(pdata->dp_lanes - 1);
>  	regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
>  			   val);
>  
> -- 
> 2.24.1.735.g03f4e72817-goog
>