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Message-ID: <556c2277-885c-f6be-60b3-564187618ca6@linux.intel.com>
Date:   Wed, 5 Feb 2020 17:10:20 +0800
From:   "Tanwar, Rahul" <rahul.tanwar@...ux.intel.com>
To:     Stephen Boyd <sboyd@...nel.org>, linux-clk@...r.kernel.org,
        mark.rutland@....com, mturquette@...libre.com, robh+dt@...nel.org,
        robh@...nel.org
Cc:     linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        andriy.shevchenko@...el.com, qi-ming.wu@...el.com,
        yixin.zhu@...ux.intel.com, cheol.yong.kim@...el.com
Subject: Re: [PATCH v4 2/2] dt-bindings: clk: intel: Add bindings document &
 header file for CGU


Hi Stephen,

Thanks for taking time out to review.

On 31/1/2020 10:25 AM, Stephen Boyd wrote:
> Quoting Rahul Tanwar (2020-01-30 01:04:03)
>> Clock generation unit(CGU) is a clock controller IP of Intel's Lightning
>> Mountain(LGM) SoC. Add DT bindings include file and document for CGU clock
>> controller driver of LGM.
>>
>> Signed-off-by: Rahul Tanwar <rahul.tanwar@...ux.intel.com>
>> ---
>>
>> +
>> +/* LJPLL4 */
>> +#define LGM_CLK_PCIE           45
>> +#define LGM_CLK_SATA           LGM_CLK_PCIE
> What is with the aliases?

Aliases are just for code readability when more than one peripherals
share the same clock.

Regards,
Rahul


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