| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Thu, 6 Feb 2020 08:02:07 +0000
From: Mubin Usman Sayyed <MUBINUSM@...inx.com>
To: Michal Simek <michals@...inx.com>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"jason@...edaemon.net" <jason@...edaemon.net>,
"maz@...nel.org" <maz@...nel.org>,
Michal Simek <michals@...inx.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Siva Durga Prasad Paladugu <sivadur@...inx.com>,
Anirudha Sarangi <anirudh@...inx.com>
Subject: RE: [PATCH v2] irqchip: xilinx: Add support for multiple instances
Hi Michal,
> -----Original Message-----
> From: Michal Simek <michal.simek@...inx.com>
> Sent: Wednesday, February 5, 2020 8:23 PM
> To: Mubin Usman Sayyed <MUBINUSM@...inx.com>; tglx@...utronix.de;
> jason@...edaemon.net; maz@...nel.org; Michal Simek
> <michals@...inx.com>; linux-arm-kernel@...ts.infradead.org
> Cc: linux-kernel@...r.kernel.org; Siva Durga Prasad Paladugu
> <sivadur@...inx.com>; Anirudha Sarangi <anirudh@...inx.com>
> Subject: Re: [PATCH v2] irqchip: xilinx: Add support for multiple instances
>
> Hi Mubin,
>
> On 05. 02. 20 15:05, Mubin Usman Sayyed wrote:
> > From: Mubin Sayyed <mubin.usman.sayyed@...inx.com>
> >
> > This patch adds support for multiple instances of xilinx interrupt
> > controller. Below configurations are supported by driver,
> >
> > - peripheral->xilinx-intc->xilinx-intc->gic
> > - peripheral->xilinx-intc->xilinx-intc
> >
> > Signed-off-by: Anirudha Sarangi <anirudha.sarangi@...inx.com>
> > Signed-off-by: Mubin Sayyed <mubin.usman.sayyed@...inx.com>
> > ---
> > Changes for v2:
> > - Removed write_fn/read_fn hooks, used xintc_write/
> > xintc_read directly
> > - Moved primary_intc declaration after xintc_irq_chip
> > ---
> > drivers/irqchip/irq-xilinx-intc.c | 121
> > +++++++++++++++++++++++---------------
> > 1 file changed, 73 insertions(+), 48 deletions(-)
> >
> > diff --git a/drivers/irqchip/irq-xilinx-intc.c
> > b/drivers/irqchip/irq-xilinx-intc.c
> > index e3043de..14cb630 100644
> > --- a/drivers/irqchip/irq-xilinx-intc.c
> > +++ b/drivers/irqchip/irq-xilinx-intc.c
> > @@ -38,29 +38,32 @@ struct xintc_irq_chip {
> > void __iomem *base;
> > struct irq_domain *root_domain;
> > u32 intr_mask;
> > + struct irq_chip *intc_dev;
> > + u32 nr_irq;
>
> indentation is weird.
[Mubin]: I will fix it in next version.
>
> > };
> >
> > -static struct xintc_irq_chip *xintc_irqc;
> > +static struct xintc_irq_chip *primary_intc;
> >
> > -static void xintc_write(int reg, u32 data)
> > +static void xintc_write(void __iomem *addr, u32 data)
>
> The best would be if prototype is
> static void xintc_write(struct xintc_irq_chip *irqc, int reg, u32 data)
[Mubin]: Agreed, will change it in next version.
>
>
> > {
> > if (static_branch_unlikely(&xintc_is_be))
> > - iowrite32be(data, xintc_irqc->base + reg);
> > + iowrite32be(data, addr);
> > else
> > - iowrite32(data, xintc_irqc->base + reg);
> > + iowrite32(data, addr);
> > }
> >
> > -static unsigned int xintc_read(int reg)
> > +static unsigned int xintc_read(void __iomem *addr)
>
> And the same here.
> static unsigned int xintc_read(struct xintc_irq_chip *irqc, int reg)
>
[Mubin]: Sure
> > {
> > if (static_branch_unlikely(&xintc_is_be))
> > - return ioread32be(xintc_irqc->base + reg);
> > + return ioread32be(addr);
> > else
> > - return ioread32(xintc_irqc->base + reg);
> > + return ioread32(addr);
> > }
> >
> > static void intc_enable_or_unmask(struct irq_data *d) {
> > unsigned long mask = 1 << d->hwirq;
> > + struct xintc_irq_chip *local_intc = irq_data_get_irq_chip_data(d);
>
> code is using variable name as irqc below. I think that will be the best to use it
> in all functions. It means s/local_intc/irqc/g'
[Mubin]: Will fix it in next version
Thanks,
Mubin
>
>
> >
> > pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq);
> >
> > @@ -69,47 +72,57 @@ static void intc_enable_or_unmask(struct irq_data
> *d)
> > * acks the irq before calling the interrupt handler
> > */
> > if (irqd_is_level_type(d))
> > - xintc_write(IAR, mask);
> > + xintc_write(local_intc->base + IAR, mask);
> >
> > - xintc_write(SIE, mask);
> > + xintc_write(local_intc->base + SIE, mask);
> > }
> >
> > static void intc_disable_or_mask(struct irq_data *d) {
> > + struct xintc_irq_chip *local_intc = irq_data_get_irq_chip_data(d);
> > +
> > pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);
> > - xintc_write(CIE, 1 << d->hwirq);
> > + xintc_write(local_intc->base + CIE, 1 << d->hwirq);
> > }
> >
> > static void intc_ack(struct irq_data *d) {
> > + struct xintc_irq_chip *local_intc = irq_data_get_irq_chip_data(d);
> > +
> > pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);
> > - xintc_write(IAR, 1 << d->hwirq);
> > + xintc_write(local_intc->base + IAR, 1 << d->hwirq);
> > }
> >
> > static void intc_mask_ack(struct irq_data *d) {
> > unsigned long mask = 1 << d->hwirq;
> > + struct xintc_irq_chip *local_intc = irq_data_get_irq_chip_data(d);
> >
> > pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);
> > - xintc_write(CIE, mask);
> > - xintc_write(IAR, mask);
> > + xintc_write(local_intc->base + CIE, mask);
> > + xintc_write(local_intc->base + IAR, mask);
> > }
> >
> > -static struct irq_chip intc_dev = {
> > - .name = "Xilinx INTC",
> > - .irq_unmask = intc_enable_or_unmask,
> > - .irq_mask = intc_disable_or_mask,
> > - .irq_ack = intc_ack,
> > - .irq_mask_ack = intc_mask_ack,
> > -};
> > +static unsigned int xintc_get_irq_local(struct xintc_irq_chip
> > +*local_intc) {
> > + int hwirq, irq = -1;
> > +
> > + hwirq = xintc_read(local_intc->base + IVR);
> > + if (hwirq != -1U)
> > + irq = irq_find_mapping(local_intc->root_domain, hwirq);
> > +
> > + pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
> > +
> > + return irq;
> > +}
> >
> > unsigned int xintc_get_irq(void)
> > {
> > - unsigned int hwirq, irq = -1;
> > + int hwirq, irq = -1;
> >
> > - hwirq = xintc_read(IVR);
> > + hwirq = xintc_read(primary_intc->base + IVR);
> > if (hwirq != -1U)
> > - irq = irq_find_mapping(xintc_irqc->root_domain, hwirq);
> > + irq = irq_find_mapping(primary_intc->root_domain, hwirq);
> >
> > pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
> >
> > @@ -118,15 +131,18 @@ unsigned int xintc_get_irq(void)
> >
> > static int xintc_map(struct irq_domain *d, unsigned int irq,
> > irq_hw_number_t hw) {
> > - if (xintc_irqc->intr_mask & (1 << hw)) {
> > - irq_set_chip_and_handler_name(irq, &intc_dev,
> > + struct xintc_irq_chip *local_intc = d->host_data;
> > +
> > + if (local_intc->intr_mask & (1 << hw)) {
> > + irq_set_chip_and_handler_name(irq, local_intc->intc_dev,
> > handle_edge_irq, "edge");
> > irq_clear_status_flags(irq, IRQ_LEVEL);
> > } else {
> > - irq_set_chip_and_handler_name(irq, &intc_dev,
> > + irq_set_chip_and_handler_name(irq, local_intc->intc_dev,
> > handle_level_irq, "level");
> > irq_set_status_flags(irq, IRQ_LEVEL);
> > }
> > + irq_set_chip_data(irq, local_intc);
> > return 0;
> > }
> >
> > @@ -138,11 +154,13 @@ static const struct irq_domain_ops
> > xintc_irq_domain_ops = { static void xil_intc_irq_handler(struct
> > irq_desc *desc) {
> > struct irq_chip *chip = irq_desc_get_chip(desc);
> > + struct xintc_irq_chip *local_intc =
> > + irq_data_get_irq_handler_data(&desc->irq_data);
> > u32 pending;
> >
> > chained_irq_enter(chip, desc);
> > do {
> > - pending = xintc_get_irq();
> > + pending = xintc_get_irq_local(local_intc);
> > if (pending == -1U)
> > break;
> > generic_handle_irq(pending);
> > @@ -153,28 +171,20 @@ static void xil_intc_irq_handler(struct irq_desc
> > *desc) static int __init xilinx_intc_of_init(struct device_node *intc,
> > struct device_node *parent) {
> > - u32 nr_irq;
> > int ret, irq;
> > struct xintc_irq_chip *irqc;
> > -
> > - if (xintc_irqc) {
> > - pr_err("irq-xilinx: Multiple instances aren't supported\n");
> > - return -EINVAL;
> > - }
> > + struct irq_chip *intc_dev;
> >
> > irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
> > if (!irqc)
> > return -ENOMEM;
> > -
> > - xintc_irqc = irqc;
> > -
> > irqc->base = of_iomap(intc, 0);
> > BUG_ON(!irqc->base);
> >
> > - ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq);
> > + ret = of_property_read_u32(intc, "xlnx,num-intr-inputs",
> > +&irqc->nr_irq);
> > if (ret < 0) {
> > pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n");
> > - goto err_alloc;
> > + goto error;
> > }
> >
> > ret = of_property_read_u32(intc, "xlnx,kind-of-intr",
> > &irqc->intr_mask); @@ -183,30 +193,42 @@ static int __init
> xilinx_intc_of_init(struct device_node *intc,
> > irqc->intr_mask = 0;
> > }
> >
> > - if (irqc->intr_mask >> nr_irq)
> > + if (irqc->intr_mask >> irqc->nr_irq)
> > pr_warn("irq-xilinx: mismatch in kind-of-intr param\n");
> >
> > pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n",
> > - intc, nr_irq, irqc->intr_mask);
> > + intc, irqc->nr_irq, irqc->intr_mask);
> > +
> > + intc_dev = kzalloc(sizeof(*intc_dev), GFP_KERNEL);
> > + if (!intc_dev) {
> > + ret = -ENOMEM;
> > + goto error;
> > + }
> >
> > + intc_dev->name = intc->full_name;
> > + intc_dev->irq_unmask = intc_enable_or_unmask,
> > + intc_dev->irq_mask = intc_disable_or_mask,
> > + intc_dev->irq_ack = intc_ack,
> > + intc_dev->irq_mask_ack = intc_mask_ack,
> > + irqc->intc_dev = intc_dev;
> >
> > /*
> > * Disable all external interrupts until they are
> > * explicity requested.
> > */
> > - xintc_write(IER, 0);
> > + xintc_write(irqc->base + IER, 0);
> >
> > /* Acknowledge any pending interrupts just in case. */
> > - xintc_write(IAR, 0xffffffff);
> > + xintc_write(irqc->base + IAR, 0xffffffff);
> >
> > /* Turn on the Master Enable. */
> > - xintc_write(MER, MER_HIE | MER_ME);
> > - if (!(xintc_read(MER) & (MER_HIE | MER_ME))) {
> > + xintc_write(irqc->base + MER, MER_HIE | MER_ME);
> > + if (!(xintc_read(irqc->base + MER) & (MER_HIE | MER_ME))) {
> > static_branch_enable(&xintc_is_be);
> > - xintc_write(MER, MER_HIE | MER_ME);
> > + xintc_write(irqc->base + MER, MER_HIE | MER_ME);
> > }
> >
> > - irqc->root_domain = irq_domain_add_linear(intc, nr_irq,
> > + irqc->root_domain = irq_domain_add_linear(intc, irqc->nr_irq,
> > &xintc_irq_domain_ops,
> irqc);
> > if (!irqc->root_domain) {
> > pr_err("irq-xilinx: Unable to create IRQ domain\n"); @@ -
> 225,13
> > +247,16 @@ static int __init xilinx_intc_of_init(struct device_node *intc,
> > goto err_alloc;
> > }
> > } else {
> > - irq_set_default_host(irqc->root_domain);
> > + primary_intc = irqc;
> > + irq_set_default_host(primary_intc->root_domain);
> > }
> >
> > return 0;
> >
> > err_alloc:
> > - xintc_irqc = NULL;
> > + kfree(intc_dev);
> > +error:
> > + iounmap(irqc->base);
> > kfree(irqc);
> > return ret;
> >
> >
>
> Thanks,
> Michal
Powered by blists - more mailing lists