| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <DB3PR0402MB3916ED6C3FCA9BCA224A5936F5180@DB3PR0402MB3916.eurprd04.prod.outlook.com>
Date: Tue, 11 Feb 2020 11:19:57 +0000
From: Anson Huang <anson.huang@....com>
To: Rob Herring <robh@...nel.org>
CC: Aisheng Dong <aisheng.dong@....com>,
"festevam@...il.com" <festevam@...il.com>,
"shawnguo@...nel.org" <shawnguo@...nel.org>,
"stefan@...er.ch" <stefan@...er.ch>,
"kernel@...gutronix.de" <kernel@...gutronix.de>,
"linus.walleij@...aro.org" <linus.walleij@...aro.org>,
"mark.rutland@....com" <mark.rutland@....com>,
"s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
dl-linux-imx <linux-imx@....com>
Subject: RE: [PATCH V3 1/3] dt-bindings: pinctrl: Convert i.MX8MQ to
json-schema
Hi, Rob
> Subject: Re: [PATCH V3 1/3] dt-bindings: pinctrl: Convert i.MX8MQ to json-
> schema
>
> On Wed, Jan 15, 2020 at 09:30:43AM +0800, Anson Huang wrote:
> > Convert the i.MX8MQ pinctrl binding to DT schema format using
> > json-schema
> >
> > Signed-off-by: Anson Huang <Anson.Huang@....com>
> > ---
> > Changes since V2:
> > - the lisence should be GPL-2.0.
> > ---
> > .../bindings/pinctrl/fsl,imx8mq-pinctrl.txt | 36 -----------
> > .../bindings/pinctrl/fsl,imx8mq-pinctrl.yaml | 69
> ++++++++++++++++++++++
> > 2 files changed, 69 insertions(+), 36 deletions(-) delete mode
> > 100644
> > Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt
> > create mode 100644
> > Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt
> > b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt
> > deleted file mode 100644
> > index 66de750..0000000
> > --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt
> > +++ /dev/null
> > @@ -1,36 +0,0 @@
> > -* Freescale IMX8MQ IOMUX Controller
> > -
> > -Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this
> > directory -for common binding part and usage.
> > -
> > -Required properties:
> > -- compatible: "fsl,imx8mq-iomuxc"
> > -- reg: should contain the base physical address and size of the
> > iomuxc
> > - registers.
> > -
> > -Required properties in sub-nodes:
> > -- fsl,pins: each entry consists of 6 integers and represents the mux
> > and config
> > - setting for one pin. The first 5 integers <mux_reg conf_reg
> > input_reg mux_val
> > - input_val> are specified using a PIN_FUNC_ID macro, which can be
> > found in
> > - imx8mq-pinfunc.h under device tree source folder. The last integer
> > CONFIG is
> > - the pad setting value like pull-up on this pin. Please refer to
> > i.MX8M Quad
> > - Reference Manual for detailed CONFIG settings.
> > -
> > -Examples:
> > -
> > -&uart1 {
> > - pinctrl-names = "default";
> > - pinctrl-0 = <&pinctrl_uart1>;
> > -};
> > -
> > -iomuxc: pinctrl@...30000 {
> > - compatible = "fsl,imx8mq-iomuxc";
> > - reg = <0x0 0x30330000 0x0 0x10000>;
> > -
> > - pinctrl_uart1: uart1grp {
> > - fsl,pins = <
> > - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
> > - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
> > - >;
> > - };
> > -};
> > diff --git
> > a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml
> > b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml
> > new file mode 100644
> > index 0000000..e010808
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yam
> > +++ l
> > @@ -0,0 +1,69 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fschemas%2Fpinctrl%2Ffsl%2Cimx8mq-
> pinctrl.yaml%23&dat
> >
> +a=02%7C01%7CAnson.Huang%40nxp.com%7C8471ec5c0f6848eafe0e08d79
> ec297db%
> >
> +7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63715243091635696
> 3&s
> >
> +data=3SEytaczKAQzAlgI3XJANKuxRjuZj0NzI8eemFoPMeU%3D&reserve
> d=0
> > +$schema:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fmeta-
> schemas%2Fcore.yaml%23&data=02%7C01%7CAnson.Hua
> >
> +ng%40nxp.com%7C8471ec5c0f6848eafe0e08d79ec297db%7C686ea1d3bc2b
> 4c6fa92
> >
> +cd99c5c301635%7C0%7C0%7C637152430916356963&sdata=V4ul%2Fq
> CNNkKXmX
> > +270HNbhYci4aTwOvTCTpD3NqQAUoQ%3D&reserved=0
> > +
> > +title: Freescale IMX8MQ IOMUX Controller
> > +
> > +maintainers:
> > + - Anson Huang <Anson.Huang@....com>
> > +
> > +description:
> > + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in
> > +this directory
> > + for common binding part and usage.
> > +
> > +properties:
> > + compatible:
> > + const: fsl,imx8mq-iomuxc
> > +
> > + reg:
> > + maxItems: 1
> > +
> > +# Client device subnode's properties
> > +patternProperties:
> > + 'grp$':
> > + type: object
> > + description:
> > + Pinctrl node's client devices use subnodes for desired pin configuration.
> > + Client device subnodes use below standard properties.
> > +
> > + properties:
> > + fsl,pins:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32-array
> > + description:
> > + each entry consists of 6 integers and represents the mux and config
> > + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
> > + mux_val input_val> are specified using a PIN_FUNC_ID macro, which
> can
> > + be found in <arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h>.
> The last
> > + integer CONFIG is the pad setting value like pull-up on this pin.
> Please
> > + refer to i.MX8M Quad Reference Manual for detailed CONFIG
> settings.
>
> Based on the description, I think this should be an uint32-matrix type instead
> with a schema like this:
>
> items:
> items:
> - description: mux_reg
> - description: conf_reg
> - description: input_reg
> - description: mux_val
> - description: input_val
> - description: pad setting
>
> (With better descriptions preferrably)
I will use something like below:
+ - $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ - items:
+ items:
+ - description: |
+ "mux_reg" indicates the offset of mux register.
+ - description: |
+ "conf_reg" indicates the offset of pad configuration register.
+ - description: |
+ "input_reg" indicates the offset of select input register.
+ - description: |
+ "mux_val" indicates the mux value to be applied.
+ - description: |
+ "input_val" gives the select input value to be applied.
+ - description: |
+ "pad_setting" gives the pad configuration value to be applied.
>
> The dts files should then be bracketed accordingly.
Sorry, what do you mean of "dts files should then be bracketed accordingly"?
Do you mean dts file needs to be updated? I saw below example already has "<>" for
This matrix:
+ fsl,pins = <
+ 0x234 0x49C 0x4F4 0x0 0x0 0x49
+ 0x238 0x4A0 0x4F4 0x0 0x0 0x49
+ >;
Can you please advise and provide a simple example, I think we should avoid changes
In dts file.
Thanks,
Anson
>
> > +
> > + required:
> > + - fsl,pins
> > +
> > + additionalProperties: false
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + # Pinmux controller node
> > + - |
> > + iomuxc: pinctrl@...30000 {
> > + compatible = "fsl,imx8mq-iomuxc";
> > + reg = <0x30330000 0x10000>;
> > +
> > + pinctrl_uart1: uart1grp {
> > + fsl,pins = <
> > + 0x234 0x49C 0x4F4 0x0 0x0 0x49
> > + 0x238 0x4A0 0x4F4 0x0 0x0 0x49
> > + >;
> > + };
> > + };
> > +
> > +...
> > --
> > 2.7.4
> >
Powered by blists - more mailing lists