linux-kernel - Re: [PATCH RFC 0/7] perf pmu-events: Support event aliasing for system PMUs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Tue, 11 Feb 2020 15:24:37 +0000
From:   James Clark <james.clark@....com>
To:     John Garry <john.garry@...wei.com>, peterz@...radead.org,
        mingo@...hat.com, acme@...nel.org, mark.rutland@....com,
        alexander.shishkin@...ux.intel.com, jolsa@...hat.com,
        namhyung@...nel.org, will@...nel.org, ak@...ux.intel.com
Cc:     linuxarm@...wei.com, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, suzuki.poulose@....com,
        zhangshaokun@...ilicon.com, robin.murphy@....com
Subject: Re: [PATCH RFC 0/7] perf pmu-events: Support event aliasing for
 system PMUs

Hi John,

I tested this on an Arm N1 board and see the same list of CPU events from the JSONs
picked up so it looks ok from that point of view.

James

On 1/24/20 2:34 PM, John Garry wrote:
> Currently event aliasing for only CPU and uncore PMUs is supported. In
> fact, only uncore PMUs aliasing for when the uncore PMUs are fixed for a
> CPU is supported, which may not always be the case for certain
> architectures.
>
> This series adds support for PMU event aliasing for system and other
> uncore PMUs which are not fixed to a specific CPU.
>
> For this, we introduce support for another per-arch mapfile, which maps a
> particular system identifier to a set of system PMU events for that
> system. This is much the same as what we do for CPU event aliasing.
>
> To support this, we need to change how we match a PMU to a mapfile,
> whether it should use a CPU or system mapfile. For this we do the
> following:
>
> - For CPU PMU, we always match for the event mapfile based on the CPUID.
>   This has not changed.
>
> - For an uncore or system PMU, we match first based on the SYSID (if set).
>   If this fails, then we match on the CPUID.
>
>   This works for x86, as x86 would not have any system mapfiles for uncore
>   PMUs (and match on the CPUID).
>
> Initial reference support is also added for ARM SMMUv3 PMCG (Performance
> Monitor Event Group) PMU for HiSilicon hip08 platform with only a single
> event so far - see driver in drivers/perf/arm_smmuv3_pmu.c for that driver.
>
> Here is a sample output with this series:
>
> root@...ntu:/# ./perf list
>   [...]
>
>   smmuv3_pmcg_100020/config_cache_miss/              [Kernel PMU event]
>   smmuv3_pmcg_100020/config_struct_access/           [Kernel PMU event]
>   smmuv3_pmcg_100020/cycles/                         [Kernel PMU event]
>   smmuv3_pmcg_100020/pcie_ats_trans_passed/          [Kernel PMU event]
>   smmuv3_pmcg_100020/pcie_ats_trans_rq/              [Kernel PMU event]
>   smmuv3_pmcg_100020/tlb_miss/                       [Kernel PMU event]
>   smmuv3_pmcg_100020/trans_table_walk_access/        [Kernel PMU event]
>   smmuv3_pmcg_100020/transaction/                    [Kernel PMU event]
>
>   [...]
>
> smmu v3 pmcg:
>   smmuv3_pmcg.l1_tlb
>        [SMMUv3 PMCG l1_tlb. Unit: smmuv3_pmcg]
>
>   [...]
>
> root@...ntu:/# ./perf stat -v -e smmuv3_pmcg.l1_tlb sleep 1
> Using CPUID 0x00000000480fd010
> Using SYSID HIP08
>  -> smmuv3_pmcg_200100020/event=0x8a/
>  -> smmuv3_pmcg_200140020/event=0x8a/
>  -> smmuv3_pmcg_100020/event=0x8a/
>  -> smmuv3_pmcg_140020/event=0x8a/
>  -> smmuv3_pmcg_200148020/event=0x8a/
>  -> smmuv3_pmcg_148020/event=0x8a/
> smmuv3_pmcg.l1_tlb: 0 1001221690 1001221690
> smmuv3_pmcg.l1_tlb: 0 1001220090 1001220090
> smmuv3_pmcg.l1_tlb: 101 1001219660 1001219660
> smmuv3_pmcg.l1_tlb: 0 1001219010 1001219010
> smmuv3_pmcg.l1_tlb: 0 1001218360 1001218360
> smmuv3_pmcg.l1_tlb: 134 1001217850 1001217850
>
>  Performance counter stats for 'system wide':
>
>                235      smmuv3_pmcg.l1_tlb
>
>        1.001263128 seconds time elapsed
>
> root@...ntu:/#
>
> Issues with this series which need to be addressed (aware to me):
>
> - It would be good to have a universal method to identify the system from
>   sysfs. Nothing exists which I know about. There is DMI, but this is not
>   always available (or has correct info). Maybe systems which want to
>   support this feature will need a "soc" driver, and a
>   /sys/devices/socX/machine file (which I used for testing this series -
>   this driver is out of tree currently).
>
> - Maybe it is ok, but for systems which match on the system identifier,
>   uncore PMUs should be in the system mapfile, and, as such, match on the
>   system identifier and not CPU identifier.
>
> - We need a better way in jevents.c to give a direct mapping of PMU name
>   aliases, i.e. for any PMU name not prefixed with "uncore_", we need to
>   add this to table unit_to_pmu[]. Not scalable.
>
>   Having said that, maybe the kernel can introduce some future PMU naming
>   convention in future.
>
> John Garry (7):
>   perf jevents: Add support for an extra directory level
>   perf vendor events arm64: Relocate hip08 core events
>   perf jevents: Add support for a system events PMU
>   perf pmu: Rename uncore symbols to include system pmus
>   perf pmu: Support matching by sysid
>   perf vendor events arm64: Relocate uncore events for hip08
>   perf vendor events arm64: Add hip08 SMMUv3 PMCG IMP DEF events
>
>  tools/perf/arch/arm64/util/arm-spe.c          |   2 +-
>  tools/perf/pmu-events/README                  |  47 ++++++--
>  .../hip08/{ => cpu}/core-imp-def.json         |   0
>  .../hisilicon/hip08/sys/smmu-v3-pmcg.json     |   9 ++
>  .../hip08/{ => sys}/uncore-ddrc.json          |   0
>  .../hisilicon/hip08/{ => sys}/uncore-hha.json |   0
>  .../hisilicon/hip08/{ => sys}/uncore-l3c.json |   0
>  tools/perf/pmu-events/arch/arm64/mapfile.csv  |   2 +-
>  .../pmu-events/arch/arm64/mapfile_sys.csv     |  14 +++
>  tools/perf/pmu-events/jevents.c               |  65 ++++++++--
>  tools/perf/pmu-events/pmu-events.h            |   1 +
>  tools/perf/util/evsel.h                       |   2 +-
>  tools/perf/util/parse-events.c                |  12 +-
>  tools/perf/util/pmu.c                         | 111 +++++++++++++++---
>  tools/perf/util/pmu.h                         |   2 +-
>  15 files changed, 221 insertions(+), 46 deletions(-)
>  rename tools/perf/pmu-events/arch/arm64/hisilicon/hip08/{ => cpu}/core-imp-def.json (100%)
>  create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/sys/smmu-v3-pmcg.json
>  rename tools/perf/pmu-events/arch/arm64/hisilicon/hip08/{ => sys}/uncore-ddrc.json (100%)
>  rename tools/perf/pmu-events/arch/arm64/hisilicon/hip08/{ => sys}/uncore-hha.json (100%)
>  rename tools/perf/pmu-events/arch/arm64/hisilicon/hip08/{ => sys}/uncore-l3c.json (100%)
>  create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile_sys.csv
>
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.